Unified Coverage Report :: Module :: prim_subreg_arb

Module : prim_subreg_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	87.50	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_state.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_pwrb_in.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_key0_in.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_key1_in.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_key2_in.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_lid_open.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_ac_present.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_ec_rst_l.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_pin_in_value_flash_wp_l.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ulp_status.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_wkup_status.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_bat_disable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_ec_rst_l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_pwrb_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_key0_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_key1_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_key2_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_z3_wakeup.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_ctl_flash_wp_l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_bat_disable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_ec_rst_l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_pwrb_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_key0_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_key1_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_key2_out.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_pre_det_ctl_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb	100.00	100.00	100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_pwrb_in.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_key0_in.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_key1_in.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_key2_in.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_lid_open.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_ac_present.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_ec_rst_l.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_pin_in_value_flash_wp_l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         0/1     ==>      assign wr_en   = de;
44         1/1              assign wr_data = d;
           Tests:       T4 T5 T6 
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_bat_disable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_ec_rst_l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_pwrb_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key0_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key1_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key2_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_z3_wakeup.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_flash_wp_l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_bat_disable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_ec_rst_l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_pwrb_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key0_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key1_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key2_out.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T5 T2 T15 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T4 T5 T6 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_regwen.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

112                       end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113        1/1              assign wr_en   = we | de;
           Tests:       T33 T34 T35 
114                         if (Mubi) begin : gen_mubi
115                           if (DW == 4) begin : gen_mubi4
116                             assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117                                                                          (we ? prim_mubi_pkg::mubi4_t'(wd) :
118                                                                                prim_mubi_pkg::MuBi4True));
119                           end else if (DW == 8) begin : gen_mubi8
120                             assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121                                                                          (we ? prim_mubi_pkg::mubi8_t'(wd) :
122                                                                                prim_mubi_pkg::MuBi8True));
123                           end else if (DW == 12) begin : gen_mubi12
124                             assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125                                                                           (we ? prim_mubi_pkg::mubi12_t'(wd) :
126                                                                                 prim_mubi_pkg::MuBi12True));
127                           end else if (DW == 16) begin : gen_mubi16
128                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129                                                                           (we ? prim_mubi_pkg::mubi16_t'(wd) :
130                                                                                 prim_mubi_pkg::MuBi16True));
131                           end else begin : gen_invalid_mubi
132                             $error("%m: Invalid width for MuBi");
133                           end
134                         end else begin : gen_non_mubi
135        1/1                assign wr_data = (de ? d : q) & (we ? wd : '1);
           Tests:       T4 T5 T6 

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_ulp_status.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_wkup_status.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

87                          // If both try to set/clr at the same bit pos, SW wins.
88         1/1              assign wr_en   = we | de;
           Tests:       T4 T5 T6 
89                          if (Mubi) begin : gen_mubi
90                            if (DW == 4) begin : gen_mubi4
91                              assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92                                                                           (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93                                                                                 prim_mubi_pkg::MuBi4True));
94                            end else if (DW == 8) begin : gen_mubi8
95                              assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96                                                                           (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97                                                                                 prim_mubi_pkg::MuBi8True));
98                            end else if (DW == 12) begin : gen_mubi12
99                              assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100                                                                           (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101                                                                                 prim_mubi_pkg::MuBi12True));
102                           end else if (DW == 16) begin : gen_mubi16
103                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104                                                                           (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105                                                                                 prim_mubi_pkg::MuBi16True));
106                           end else begin : gen_invalid_mubi
107                             $error("%m: Invalid width for MuBi");
108                           end
109                         end else begin : gen_non_mubi
110        1/1                assign wr_data = (de ? d : q) & (we ? ~wd : '1);
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_status.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_wkup_status.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T8

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_debounce_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_debounce_timer.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T5,T1,T2

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T1,T2

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T1,T2

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_bat_disable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_ec_rst_l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_pwrb_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key0_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key1_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_key2_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_z3_wakeup.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_ctl_flash_wp_l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_bat_disable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_ec_rst_l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_pwrb_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key0_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key1_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_key2_out.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_z3_wakeup.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_pin_out_value_flash_wp_l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_pwrb_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key0_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key1_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key2_in_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ac_present_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_h2l.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_pwrb_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key0_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key1_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_key2_in_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ac_present_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_ec_rst_l_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_key_intr_ctl_flash_wp_l_l2h.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_debounce_ctl_auto_block_enable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key0_out_sel.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key1_out_sel.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key2_out_sel.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key0_out_value.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key1_out_value.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_auto_block_out_ctl_key2_out_value.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key0_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key1_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_key2_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_0_ac_present_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key0_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key1_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_key2_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_1_ac_present_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key0_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key1_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_key2_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_2_ac_present_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key0_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key1_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_key2_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_sel_ctl_3_ac_present_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key0_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key1_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_key2_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_pwrb_in_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_0_ac_present_sel_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key0_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key1_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_key2_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_pwrb_in_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_1_ac_present_sel_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key0_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key1_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_key2_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_pwrb_in_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_2_ac_present_sel_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key0_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key1_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_key2_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_pwrb_in_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_sel_ctl_3_ac_present_sel_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T15,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_regwen.wr_en_data_arb

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T33,T34,T35

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T35,T36,T37
1	1	Covered	T4,T5,T6

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T34,T35

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_pre_det_ctl_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T5,T2,T32

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T2,T32

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T2,T32

---

Branch Coverage for Module : prim_subreg_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T3
0	Covered	T4,T5,T6