Unified Coverage Report :: Module :: sysrst_ctrl_pin

Module : sysrst_ctrl_pin

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_pin	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_pin

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cfg_ac_present_i_pin	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_pin

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	147	1	1	100.00

90                        logic [NumSignals-1:0] inputs, outputs, aon_enabled, aon_values, aon_allowed0, aon_allowed1;
91         1/1            assign inputs = {
           Tests:       T4 T5 T6 
92                          pwrb_out_hw_i,
93                          key0_out_hw_i,
94                          key1_out_hw_i,
95                          key2_out_hw_i,
96                          aon_z3_wakeup_hw_i,
97                          aon_bat_disable_hw_i,
98                          aon_ec_rst_l_hw_i,
99                          1'b0 // there is no pass through input value for this signal.
100                       };
101        1/1            assign aon_enabled = {
           Tests:       T5 T6 T2 
102                         aon_pin_out_ctl_i.pwrb_out.q,
103                         aon_pin_out_ctl_i.key0_out.q,
104                         aon_pin_out_ctl_i.key1_out.q,
105                         aon_pin_out_ctl_i.key2_out.q,
106                         aon_pin_out_ctl_i.z3_wakeup.q,
107                         aon_pin_out_ctl_i.bat_disable.q,
108                         aon_pin_out_ctl_i.ec_rst_l.q,
109                         aon_pin_out_ctl_i.flash_wp_l.q
110                       };
111        1/1            assign aon_values = {
           Tests:       T6 T15 T27 
112                         aon_pin_out_value_i.pwrb_out.q,
113                         aon_pin_out_value_i.key0_out.q,
114                         aon_pin_out_value_i.key1_out.q,
115                         aon_pin_out_value_i.key2_out.q,
116                         aon_pin_out_value_i.z3_wakeup.q,
117                         aon_pin_out_value_i.bat_disable.q,
118                         aon_pin_out_value_i.ec_rst_l.q,
119                         aon_pin_out_value_i.flash_wp_l.q
120                       };
121        1/1            assign aon_allowed0 = {
           Tests:       T6 T15 T16 
122                         aon_pin_allowed_ctl_i.pwrb_out_0.q,
123                         aon_pin_allowed_ctl_i.key0_out_0.q,
124                         aon_pin_allowed_ctl_i.key1_out_0.q,
125                         aon_pin_allowed_ctl_i.key2_out_0.q,
126                         aon_pin_allowed_ctl_i.z3_wakeup_0.q,
127                         aon_pin_allowed_ctl_i.bat_disable_0.q,
128                         aon_pin_allowed_ctl_i.ec_rst_l_0.q,
129                         aon_pin_allowed_ctl_i.flash_wp_l_0.q
130                       };
131        1/1            assign aon_allowed1 = {
           Tests:       T6 T15 T27 
132                         aon_pin_allowed_ctl_i.pwrb_out_1.q,
133                         aon_pin_allowed_ctl_i.key0_out_1.q,
134                         aon_pin_allowed_ctl_i.key1_out_1.q,
135                         aon_pin_allowed_ctl_i.key2_out_1.q,
136                         aon_pin_allowed_ctl_i.z3_wakeup_1.q,
137                         aon_pin_allowed_ctl_i.bat_disable_1.q,
138                         aon_pin_allowed_ctl_i.ec_rst_l_1.q,
139                         aon_pin_allowed_ctl_i.flash_wp_l_1.q
140                       };
141                     
142                       for (genvar k = 0; k < NumSignals; k++) begin : gen_override_logic
143        8/8              assign outputs[k] = (aon_enabled[k] && aon_allowed0[k] && !aon_values[k]) ? 1'b0 :
           Tests:       T6 T15 T16  | T5 T6 T2  | T6 T15 T27  | T6 T15 T3  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T6 T1 
144                                             (aon_enabled[k] && aon_allowed1[k] &&  aon_values[k]) ? 1'b1 : inputs[k];
145                       end
146                     
147        1/1            assign {pwrb_out_int_o,
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : sysrst_ctrl_pin

	Total	Covered	Percent
Conditions	96	96	100.00
Logical	96	96	100.00
Non-Logical	0	0
Event	0	0

 LINE       143
 EXPRESSION ((aon_enabled[0] && aon_allowed0[0] && ((!aon_values[0]))) ? 1'b0 : ((aon_enabled[0] && aon_allowed1[0] && aon_values[0]) ? 1'b1 : inputs[0]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T6,T15,T16
1	Covered	T4,T5,T6

 LINE       143
 SUB-EXPRESSION (aon_enabled[0] && aon_allowed0[0] && ((!aon_values[0])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T4,T5,T6

 LINE       143
 SUB-EXPRESSION ((aon_enabled[0] && aon_allowed1[0] && aon_values[0]) ? 1'b1 : inputs[0])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T6,T15,T16
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[0] && aon_allowed1[0] && aon_values[0])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T6,T15,T27

 LINE       143
 EXPRESSION ((aon_enabled[1] && aon_allowed0[1] && ((!aon_values[1]))) ? 1'b0 : ((aon_enabled[1] && aon_allowed1[1] && aon_values[1]) ? 1'b1 : inputs[1]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T4,T5,T6

 LINE       143
 SUB-EXPRESSION (aon_enabled[1] && aon_allowed0[1] && ((!aon_values[1])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T2
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T15,T27,T67
1	1	1	Covered	T4,T5,T6

 LINE       143
 SUB-EXPRESSION ((aon_enabled[1] && aon_allowed1[1] && aon_values[1]) ? 1'b1 : inputs[1])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[1] && aon_allowed1[1] && aon_values[1])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T6,T15,T27

 LINE       143
 EXPRESSION ((aon_enabled[2] && aon_allowed0[2] && ((!aon_values[2]))) ? 1'b0 : ((aon_enabled[2] && aon_allowed1[2] && aon_values[2]) ? 1'b1 : inputs[2]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T67

 LINE       143
 SUB-EXPRESSION (aon_enabled[2] && aon_allowed0[2] && ((!aon_values[2])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T6,T15,T67

 LINE       143
 SUB-EXPRESSION ((aon_enabled[2] && aon_allowed1[2] && aon_values[2]) ? 1'b1 : inputs[2])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[2] && aon_allowed1[2] && aon_values[2])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T15,T27,T67
1	1	1	Covered	T6,T15,T27

 LINE       143
 EXPRESSION ((aon_enabled[3] && aon_allowed0[3] && ((!aon_values[3]))) ? 1'b0 : ((aon_enabled[3] && aon_allowed1[3] && aon_values[3]) ? 1'b1 : inputs[3]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[3] && aon_allowed0[3] && ((!aon_values[3])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION ((aon_enabled[3] && aon_allowed1[3] && aon_values[3]) ? 1'b1 : inputs[3])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[3] && aon_allowed1[3] && aon_values[3])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T6,T15,T27

 LINE       143
 EXPRESSION ((aon_enabled[4] && aon_allowed0[4] && ((!aon_values[4]))) ? 1'b0 : ((aon_enabled[4] && aon_allowed1[4] && aon_values[4]) ? 1'b1 : inputs[4]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[4] && aon_allowed0[4] && ((!aon_values[4])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T27,T67
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION ((aon_enabled[4] && aon_allowed1[4] && aon_values[4]) ? 1'b1 : inputs[4])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[4] && aon_allowed1[4] && aon_values[4])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T6,T27,T67
1	1	1	Covered	T6,T15,T27

 LINE       143
 EXPRESSION ((aon_enabled[5] && aon_allowed0[5] && ((!aon_values[5]))) ? 1'b0 : ((aon_enabled[5] && aon_allowed1[5] && aon_values[5]) ? 1'b1 : inputs[5]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[5] && aon_allowed0[5] && ((!aon_values[5])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION ((aon_enabled[5] && aon_allowed1[5] && aon_values[5]) ? 1'b1 : inputs[5])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[5] && aon_allowed1[5] && aon_values[5])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T27,T67
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T6,T15,T27

 LINE       143
 EXPRESSION ((aon_enabled[6] && aon_allowed0[6] && ((!aon_values[6]))) ? 1'b0 : ((aon_enabled[6] && aon_allowed1[6] && aon_values[6]) ? 1'b1 : inputs[6]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[6] && aon_allowed0[6] && ((!aon_values[6])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T27,T67
1	0	1	Covered	T6,T27,T67
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION ((aon_enabled[6] && aon_allowed1[6] && aon_values[6]) ? 1'b1 : inputs[6])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[6] && aon_allowed1[6] && aon_values[6])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T6,T27,T67
1	1	1	Covered	T6,T15,T27

 LINE       143
 EXPRESSION ((aon_enabled[7] && aon_allowed0[7] && ((!aon_values[7]))) ? 1'b0 : ((aon_enabled[7] && aon_allowed1[7] && aon_values[7]) ? 1'b1 : inputs[7]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[7] && aon_allowed0[7] && ((!aon_values[7])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T27
1	0	1	Covered	T6,T15,T27
1	1	0	Covered	T6,T15,T27
1	1	1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION ((aon_enabled[7] && aon_allowed1[7] && aon_values[7]) ? 1'b1 : inputs[7])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T15,T27

 LINE       143
 SUB-EXPRESSION (aon_enabled[7] && aon_allowed1[7] && aon_values[7])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T15,T67
1	0	1	Covered	T6,T15,T67
1	1	0	Covered	T6,T27,T67
1	1	1	Covered	T6,T15,T27

---

Branch Coverage for Module : sysrst_ctrl_pin

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00

143            assign outputs[k] = (aon_enabled[k] && aon_allowed0[k] && !aon_values[k]) ? 1'b0 :
                                                                                         -1-  
                                                                                         ==>  
144                                (aon_enabled[k] && aon_allowed1[k] &&  aon_values[k]) ? 1'b1 : inputs[k];
                                                                                         -2-  
                                                                                         ==>  
                                                                                         ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T6,T15,T27
0	0	Covered	T6,T15,T16

143            assign outputs[k] = (aon_enabled[k] && aon_allowed0[k] && !aon_values[k]) ? 1'b0 :
                                                                                         -1-  
                                                                                         ==>  
144                                (aon_enabled[k] && aon_allowed1[k] &&  aon_values[k]) ? 1'b1 : inputs[k];
                                                                                         -2-  
                                                                                         ==>  
                                                                                         ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T6,T15,T27
0	0	Covered	T5,T6,T2

143            assign outputs[k] = (aon_enabled[k] && aon_allowed0[k] && !aon_values[k]) ? 1'b0 :
                                                                                         -1-  
                                                                                         ==>  
144                                (aon_enabled[k] && aon_allowed1[k] &&  aon_values[k]) ? 1'b1 : inputs[k];
                                                                                         -2-  
                                                                                         ==>  
                                                                                         ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T67
0	1	Covered	T6,T15,T27
0	0	Covered	T4,T5,T6

143            assign outputs[k] = (aon_enabled[k] && aon_allowed0[k] && !aon_values[k]) ? 1'b0 :
                                                                                         -1-  
                                                                                         ==>  
144                                (aon_enabled[k] && aon_allowed1[k] &&  aon_values[k]) ? 1'b1 : inputs[k];
                                                                                         -2-  
                                                                                         ==>  
                                                                                         ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T27
0	1	Covered	T6,T15,T27
0	0	Covered	T4,T5,T6

143            assign outputs[k] = (aon_enabled[k] && aon_allowed0[k] && !aon_values[k]) ? 1'b0 :
                                                                                         -1-  
                                                                                         ==>  
144                                (aon_enabled[k] && aon_allowed1[k] &&  aon_values[k]) ? 1'b1 : inputs[k];
                                                                                         -2-  
                                                                                         ==>  
                                                                                         ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T27
0	1	Covered	T6,T15,T27
0	0	Covered	T4,T5,T6

143            assign outputs[k] = (aon_enabled[k] && aon_allowed0[k] && !aon_values[k]) ? 1'b0 :
                                                                                         -1-  
                                                                                         ==>  
144                                (aon_enabled[k] && aon_allowed1[k] &&  aon_values[k]) ? 1'b1 : inputs[k];
                                                                                         -2-  
                                                                                         ==>  
                                                                                         ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T27
0	1	Covered	T6,T15,T27
0	0	Covered	T4,T5,T6

143            assign outputs[k] = (aon_enabled[k] && aon_allowed0[k] && !aon_values[k]) ? 1'b0 :
                                                                                         -1-  
                                                                                         ==>  
144                                (aon_enabled[k] && aon_allowed1[k] &&  aon_values[k]) ? 1'b1 : inputs[k];
                                                                                         -2-  
                                                                                         ==>  
                                                                                         ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T27
0	1	Covered	T6,T15,T27
0	0	Covered	T4,T5,T6

143            assign outputs[k] = (aon_enabled[k] && aon_allowed0[k] && !aon_values[k]) ? 1'b0 :
                                                                                         -1-  
                                                                                         ==>  
144                                (aon_enabled[k] && aon_allowed1[k] &&  aon_values[k]) ? 1'b1 : inputs[k];
                                                                                         -2-  
                                                                                         ==>  
                                                                                         ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T27
0	1	Covered	T6,T15,T27
0	0	Covered	T4,T5,T6