Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_pin_in_value_cg
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Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_pin_in_value_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_pin_in_value_cg 100.00 1 100 1 64 64



Group Instance : sysrst_ctrl_pin_in_value_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance sysrst_ctrl_pin_in_value_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 0 16 100.00


Variables for Group Instance sysrst_ctrl_pin_in_value_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_ac_present 2 0 2 100.00 100 1 1 2
cp_ec_rst_l 2 0 2 100.00 100 1 1 2
cp_flash_wp_l 2 0 2 100.00 100 1 1 2
cp_key0_in 2 0 2 100.00 100 1 1 2
cp_key1_in 2 0 2 100.00 100 1 1 2
cp_key2_in 2 0 2 100.00 100 1 1 2
cp_lid_open 2 0 2 100.00 100 1 1 2
cp_pwrb_in 2 0 2 100.00 100 1 1 2


Summary for Variable cp_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 903 1 T26 4 T14 6 T212 25
auto[1] 850 1 T26 1 T14 10 T212 16


Summary for Variable cp_ec_rst_l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 849 1 T26 2 T14 7 T212 23
auto[1] 904 1 T26 3 T14 9 T212 18


Summary for Variable cp_flash_wp_l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 886 1 T26 2 T14 7 T212 15
auto[1] 867 1 T26 3 T14 9 T212 26


Summary for Variable cp_key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 869 1 T26 5 T14 8 T212 24
auto[1] 884 1 T14 8 T212 17 T92 30


Summary for Variable cp_key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 872 1 T26 2 T14 12 T212 19
auto[1] 881 1 T26 3 T14 4 T212 22


Summary for Variable cp_key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 869 1 T26 3 T14 4 T212 16
auto[1] 884 1 T26 2 T14 12 T212 25


Summary for Variable cp_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 881 1 T26 2 T14 9 T212 20
auto[1] 872 1 T26 3 T14 7 T212 21


Summary for Variable cp_pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 887 1 T26 3 T14 8 T212 23
auto[1] 866 1 T26 2 T14 8 T212 18

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