Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1884

1

T21

19

T46

1

T98

16

auto[1]

528

1

T21

5

T46

5

T50

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1862

1

T21

17

T46

2

T98

16

auto[1]

550

1

T21

7

T46

4

T65

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1849

1

T21

24

T46

3

T98

12

auto[1]

563

1

T46

3

T98

4

T65

9

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1895

1

T21

19

T98

12

T65

9

auto[1]

517

1

T21

5

T46

6

T98

4

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2190

1

T21

22

T46

6

T98

16

auto[1]

222

1

T21

2

T99

8

T157

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2206

1

T21

24

T46

6

T98

12

auto[1]

206

1

T98

4

T157

6

T115

7

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2190

1

T21

12

T46

6

T98

16

auto[1]

222

1

T21

12

T157

6

T51

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2221

1

T21

24

T46

6

T98

16

auto[1]

191

1

T48

8

T157

3

T405

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2223

1

T21

14

T46

6

T98

16

auto[1]

189

1

T21

10

T157

9

T300

21

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1808

1

T21

22

T98

16

T65

9

auto[1]

604

1

T21

2

T46

6

T50

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

720

1

T46

6

T65

9

T49

6

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

71

1

T115

2

T388

4

T272

22

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T300

12

T388

4

T397

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T397

6

T394

4

T406

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

65

1

T48

8

T405

3

T179

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T407

6

T401

2

T408

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T157

3

T409

5

T407

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T246

7

T402

2

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

60

1

T309

2

T410

10

T409

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T21

2

T411

3

T412

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

27

1

T21

10

T157

3

T402

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T157

1

T413

1

T400

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

13

1

T414

4

T415

1

T416

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T410

1

T414

2

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T417

1

T418

2

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T407

2

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

76

1

T157

5

T309

1

T397

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T115

2

T117

6

T51

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

17

1

T413

2

T417

3

T419

12

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

20

1

T388

1

T410

4

T406

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T302

3

T420

2

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T421

3

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

27

1

T179

2

T394

4

T411

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T51

1

T272

5

T411

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T422

3

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

56

1

T309

1

T423

8

T424

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

155

1

T82

8

T48

4

T156

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T82

4

T309

1

T405

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

92

1

T156

13

T310

11

T394

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

54

1

T21

5

T171

4

T124

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T425

2

T391

5

T272

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T179

2

T387

2

T426

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

125

1

T65

6

T308

8

T310

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

52

1

T80

4

T157

5

T391

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

73

1

T156

5

T237

5

T323

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T325

3

T237

2

T323

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T51

2

T306

5

T427

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T171

4

T228

3

T307

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

30

1

T47

2

T325

5

T171

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T46

2

T309

1

T125

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

83

1

T21

5

T157

3

T124

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

56

1

T300

4

T426

4

T428

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T21

2

T391

6

T410

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T48

4

T425

2

T409

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T157

4

T387

1

T388

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

35

1

T80

5

T237

3

T322

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

12

1

T322

3

T324

2

T425

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T46

3

T322

2

T283

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T65

3

T49

6

T115

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T82

4

T283

3

T428

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T47

2

T308

1

T324

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T259

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

20

1

T80

1

T219

7

T429

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T50

2

T300

4

T390

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T46

1

T47

1

T325

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T50

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded