Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

628

1

T24

9

T81

7

T91

10

auto[1]

672

1

T24

11

T81

13

T91

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

307

1

T24

4

T81

6

T91

4

from_0to1

315

1

T24

4

T81

6

T91

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

662

1

T24

13

T81

14

T91

10

auto[1]

638

1

T24

7

T81

6

T91

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

656

1

T24

11

T81

10

T91

9

auto[1]

644

1

T24

9

T81

10

T91

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

34

1

T81

1

T91

1

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

34

1

T24

1

T81

1

T91

1

auto[0]

from_1to0

auto[1]

auto[0]

36

1

T79

2

T186

1

T256

1

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T24

1

T79

1

T186

2

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T24

1

T94

1

T79

1

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T24

1

T91

1

T94

1

auto[0]

from_0to1

auto[1]

auto[0]

33

1

T81

2

T94

1

T79

1

auto[0]

from_0to1

auto[1]

auto[1]

35

1

T91

1

T79

2

T257

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T24

1

T81

1

T79

3

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T24

1

T81

1

T91

2

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T81

1

T94

2

T79

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T81

1

T94

1

T357

1

auto[1]

from_0to1

auto[0]

auto[0]

44

1

T24

1

T81

1

T94

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T81

2

T91

1

T79

1

auto[1]

from_0to1

auto[1]

auto[0]

30

1

T24

1

T257

1

T269

1

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T81

1

T91

1

T357

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T24

9

T81

12

T91

5

auto[1]

653

1

T24

11

T81

8

T91

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

315

1

T24

5

T81

6

T91

4

from_0to1

319

1

T24

5

T81

6

T91

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

631

1

T24

9

T81

9

T91

11

auto[1]

669

1

T24

11

T81

11

T91

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659

1

T24

10

T81

11

T91

13

auto[1]

641

1

T24

10

T81

9

T91

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

37

1

T24

2

T81

2

T94

1

auto[0]

from_1to0

auto[0]

auto[1]

43

1

T81

1

T79

4

T201

2

auto[0]

from_1to0

auto[1]

auto[0]

29

1

T24

1

T81

1

T91

1

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T24

1

T94

2

T79

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T81

1

T91

1

T94

2

auto[0]

from_0to1

auto[0]

auto[1]

35

1

T24

1

T91

1

T79

3

auto[0]

from_0to1

auto[1]

auto[0]

35

1

T81

1

T201

4

T256

1

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T81

1

T256

2

T357

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T81

1

T91

1

T94

1

auto[1]

from_1to0

auto[0]

auto[1]

30

1

T256

1

T257

1

T269

1

auto[1]

from_1to0

auto[1]

auto[0]

42

1

T24

1

T81

1

T91

1

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T91

1

T186

1

T201

1

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T24

1

T94

2

T79

1

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T81

2

T79

4

T186

1

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T24

2

T91

1

T94

1

auto[1]

from_0to1

auto[1]

auto[1]

45

1

T24

1

T81

1

T91

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

677

1

T24

10

T81

8

T91

9

auto[1]

623

1

T24

10

T81

12

T91

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

300

1

T24

5

T81

3

T91

5

from_0to1

309

1

T24

5

T81

3

T91

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620

1

T24

7

T81

16

T91

10

auto[1]

680

1

T24

13

T81

4

T91

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

655

1

T24

6

T81

9

T91

12

auto[1]

645

1

T24

14

T81

11

T91

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T94

1

T186

1

T256

1

auto[0]

from_1to0

auto[0]

auto[1]

31

1

T94

1

T79

1

T186

2

auto[0]

from_1to0

auto[1]

auto[0]

41

1

T24

1

T91

1

T79

3

auto[0]

from_1to0

auto[1]

auto[1]

38

1

T94

1

T79

1

T257

2

auto[0]

from_0to1

auto[0]

auto[0]

46

1

T91

1

T94

1

T186

1

auto[0]

from_0to1

auto[0]

auto[1]

32

1

T24

1

T91

2

T94

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T24

1

T79

2

T186

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T24

2

T79

1

T186

2

auto[1]

from_1to0

auto[0]

auto[0]

34

1

T24

1

T81

2

T91

1

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T24

1

T81

1

T91

1

auto[1]

from_1to0

auto[1]

auto[0]

38

1

T91

1

T79

1

T186

1

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T24

2

T91

1

T79

1

auto[1]

from_0to1

auto[0]

auto[0]

29

1

T91

1

T79

1

T186

1

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T24

1

T81

3

T186

1

auto[1]

from_0to1

auto[1]

auto[0]

33

1

T91

1

T94

1

T357

1

auto[1]

from_0to1

auto[1]

auto[1]

38

1

T91

1

T94

1

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

681

1

T24

11

T81

12

T91

10

auto[1]

619

1

T24

9

T81

8

T91

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

307

1

T24

4

T81

5

T91

5

from_0to1

301

1

T24

4

T81

4

T91

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

655

1

T24

13

T81

14

T91

10

auto[1]

645

1

T24

7

T81

6

T91

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

621

1

T24

10

T81

8

T91

7

auto[1]

679

1

T24

10

T81

12

T91

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

35

1

T24

1

T94

1

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T81

2

T79

2

T201

1

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T79

2

T256

1

T150

2

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T81

1

T91

1

T94

1

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T186

1

T257

1

T269

1

auto[0]

from_0to1

auto[0]

auto[1]

37

1

T24

1

T81

1

T91

1

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T24

1

T91

1

T79

2

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T91

1

T94

1

T79

1

auto[1]

from_1to0

auto[0]

auto[0]

33

1

T24

1

T81

1

T91

1

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T24

2

T81

1

T91

1

auto[1]

from_1to0

auto[1]

auto[0]

42

1

T91

1

T256

1

T257

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T91

1

T79

1

T186

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T24

1

T81

1

T94

1

auto[1]

from_0to1

auto[0]

auto[1]

37

1

T91

1

T94

1

T79

2

auto[1]

from_0to1

auto[1]

auto[0]

30

1

T186

2

T256

1

T357

2

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T24

1

T81

2

T94

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

658

1

T24

13

T81

7

T91

8

auto[1]

642

1

T24

7

T81

13

T91

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

319

1

T24

5

T81

4

T91

5

from_0to1

308

1

T24

6

T81

5

T91

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

651

1

T24

9

T81

10

T91

10

auto[1]

649

1

T24

11

T81

10

T91

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645

1

T24

12

T81

11

T91

11

auto[1]

655

1

T24

8

T81

9

T91

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T81

1

T91

1

T94

1

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T79

4

T201

1

T357

2

auto[0]

from_1to0

auto[1]

auto[0]

36

1

T24

1

T81

1

T91

1

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T24

1

T91

1

T94

2

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T24

2

T81

1

T79

1

auto[0]

from_0to1

auto[0]

auto[1]

35

1

T81

1

T94

3

T79

1

auto[0]

from_0to1

auto[1]

auto[0]

34

1

T24

2

T79

2

T256

2

auto[0]

from_0to1

auto[1]

auto[1]

42

1

T91

1

T79

2

T186

1

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T24

1

T91

1

T201

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T24

1

T81

1

T94

1

auto[1]

from_1to0

auto[1]

auto[0]

38

1

T81

1

T91

1

T79

1

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T24

1

T94

1

T186

3

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T24

1

T91

1

T94

2

auto[1]

from_0to1

auto[0]

auto[1]

39

1

T24

1

T81

2

T94

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T81

1

T91

2

T94

1

auto[1]

from_0to1

auto[1]

auto[1]

32

1

T91

1

T94

1

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

649

1

T24

10

T81

8

T91

11

auto[1]

651

1

T24

10

T81

12

T91

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

307

1

T24

5

T81

6

T91

5

from_0to1

308

1

T24

4

T81

5

T91

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

635

1

T24

14

T81

10

T91

9

auto[1]

665

1

T24

6

T81

10

T91

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

690

1

T24

11

T81

12

T91

7

auto[1]

610

1

T24

9

T81

8

T91

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T24

2

T94

1

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

29

1

T24

1

T94

1

T79

1

auto[0]

from_1to0

auto[1]

auto[0]

38

1

T91

1

T79

2

T186

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T81

1

T91

1

T94

2

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T81

2

T91

1

T447

1

auto[0]

from_0to1

auto[0]

auto[1]

29

1

T24

2

T91

1

T256

1

auto[0]

from_0to1

auto[1]

auto[0]

40

1

T91

1

T94

2

T79

2

auto[0]

from_0to1

auto[1]

auto[1]

48

1

T81

1

T79

2

T201

1

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T24

1

T81

3

T79

2

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T24

1

T81

1

T91

2

auto[1]

from_1to0

auto[1]

auto[0]

33

1

T79

1

T201

1

T256

1

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T81

1

T91

1

T79

1

auto[1]

from_0to1

auto[0]

auto[0]

37

1

T24

1

T81

1

T94

2

auto[1]

from_0to1

auto[0]

auto[1]

31

1

T91

1

T79

3

T186

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T81

1

T91

1

T79

2

auto[1]

from_0to1

auto[1]

auto[1]

38

1

T24

1

T91

1

T94

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

656

1

T24

14

T81

9

T91

15

auto[1]

644

1

T24

6

T81

11

T91

5

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

303

1

T24

4

T81

4

T91

7

from_0to1

308

1

T24

3

T81

5

T91

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659

1

T24

11

T81

13

T91

9

auto[1]

641

1

T24

9

T81

7

T91

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T24

8

T81

10

T91

10

auto[1]

658

1

T24

12

T81

10

T91

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T91

2

T79

1

T186

2

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T81

1

T91

2

T94

2

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T24

1

T81

1

T91

2

auto[0]

from_1to0

auto[1]

auto[1]

27

1

T24

1

T256

1

T150

2

auto[0]

from_0to1

auto[0]

auto[0]

45

1

T91

1

T79

2

T256

1

auto[0]

from_0to1

auto[0]

auto[1]

34

1

T24

1

T81

1

T201

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T24

1

T91

2

T79

2

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T81

1

T91

2

T94

2

auto[1]

from_1to0

auto[0]

auto[0]

36

1

T79

3

T201

1

T256

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T24

1

T81

1

T94

1

auto[1]

from_1to0

auto[1]

auto[0]

32

1

T81

1

T186

1

T256

2

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T24

1

T91

1

T94

2

auto[1]

from_0to1

auto[0]

auto[0]

25

1

T24

1

T81

1

T91

1

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T81

1

T94

1

T79

2

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T81

1

T94

1

T79

3

auto[1]

from_0to1

auto[1]

auto[1]

36

1

T91

1

T79

2

T257

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

650

1

T24

13

T81

10

T91

11

auto[1]

650

1

T24

7

T81

10

T91

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

325

1

T24

4

T81

5

T91

4

from_0to1

327

1

T24

5

T81

4

T91

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

636

1

T24

12

T81

10

T91

11

auto[1]

664

1

T24

8

T81

10

T91

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

641

1

T24

6

T81

15

T91

10

auto[1]

659

1

T24

14

T81

5

T91

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T24

2

T91

1

T94

1

auto[0]

from_1to0

auto[0]

auto[1]

35

1

T24

2

T81

1

T79

1

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T91

1

T94

1

T79

2

auto[0]

from_1to0

auto[1]

auto[1]

37

1

T186

1

T201

1

T256

1

auto[0]

from_0to1

auto[0]

auto[0]

30

1

T81

1

T79

3

T186

1

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T24

2

T91

1

T79

3

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T24

1

T94

1

T79

1

auto[0]

from_0to1

auto[1]

auto[1]

37

1

T24

1

T81

1

T91

1

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T81

3

T91

1

T79

2

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T94

2

T79

3

T201

2

auto[1]

from_1to0

auto[1]

auto[0]

36

1

T81

1

T186

2

T447

1

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T91

1

T79

1

T186

1

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T79

1

T186

2

T256

1

auto[1]

from_0to1

auto[0]

auto[1]

39

1

T24

1

T91

1

T94

1

auto[1]

from_0to1

auto[1]

auto[0]

42

1

T81

2

T94

1

T79

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T91

1

T79

1

T201

1