Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

112695

1

T4

4

T5

17

T6

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136153	1			T4	3		T5	22		T6	8
values[0x0]	60260	1			T4	3		T5	10		T6	1
values[0x1]	61226	1			T4	3		T5	12		T6	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	116551	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141088

1

T4

5

T5

20

T6

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1139	1			T92	3		T34	3		T11	1
valid_sources[0x01]	884	1			T24	2		T2	1		T92	1
valid_sources[0x02]	980	1			T24	1		T83	1		T40	1
valid_sources[0x03]	1747	1			T4	9		T5	1		T2	1
valid_sources[0x04]	908	1			T92	2		T40	1		T34	3
valid_sources[0x05]	783	1			T66	1		T94	2		T87	1
valid_sources[0x06]	816	1			T14	1		T34	1		T79	2
valid_sources[0x07]	910	1			T81	2		T33	1		T92	5
valid_sources[0x08]	846	1			T16	1		T92	1		T34	1
valid_sources[0x09]	800	1			T87	1		T34	1		T79	1
valid_sources[0x0a]	936	1			T5	1		T81	1		T92	6
valid_sources[0x0b]	892	1			T24	3		T81	2		T96	20
valid_sources[0x0c]	989	1			T24	3		T16	1		T17	6
valid_sources[0x0d]	920	1			T5	1		T92	4		T34	2
valid_sources[0x0e]	1230	1			T5	2		T11	1		T77	1
valid_sources[0x0f]	1158	1			T20	1		T81	3		T96	2
valid_sources[0x10]	777	1			T96	3		T34	2		T41	1
valid_sources[0x11]	897	1			T24	3		T96	15		T92	3
valid_sources[0x12]	983	1			T5	1		T95	2		T34	1
valid_sources[0x13]	913	1			T14	2		T92	2		T34	2
valid_sources[0x14]	941	1			T5	1		T24	1		T96	7
valid_sources[0x15]	833	1			T81	3		T92	3		T40	1
valid_sources[0x16]	970	1			T7	1		T92	1		T87	1
valid_sources[0x17]	1001	1			T24	1		T2	2		T92	2
valid_sources[0x18]	2062	1			T81	2		T92	1		T95	1
valid_sources[0x19]	1046	1			T1	1		T81	1		T87	2
valid_sources[0x1a]	974	1			T16	1		T40	1		T34	2
valid_sources[0x1b]	1089	1			T5	1		T37	44		T33	2
valid_sources[0x1c]	1077	1			T92	1		T34	1		T79	1
valid_sources[0x1d]	905	1			T36	3		T96	2		T92	1
valid_sources[0x1e]	744	1			T7	1		T92	2		T40	1
valid_sources[0x1f]	796	1			T92	1		T222	1		T34	1
valid_sources[0x20]	776	1			T34	1		T41	13		T21	1
valid_sources[0x21]	934	1			T96	7		T92	1		T95	1
valid_sources[0x22]	814	1			T34	2		T74	1		T41	1
valid_sources[0x23]	1030	1			T24	1		T92	1		T34	2
valid_sources[0x24]	908	1			T2	3		T34	2		T79	1
valid_sources[0x25]	1007	1			T14	1		T18	62		T96	2
valid_sources[0x26]	887	1			T81	3		T92	1		T87	1
valid_sources[0x27]	849	1			T24	2		T2	2		T81	1
valid_sources[0x28]	834	1			T5	2		T81	1		T87	1
valid_sources[0x29]	881	1			T81	3		T92	1		T34	1
valid_sources[0x2a]	883	1			T7	1		T92	1		T8	2
valid_sources[0x2b]	1465	1			T5	1		T24	3		T1	1
valid_sources[0x2c]	936	1			T14	1		T92	2		T40	1
valid_sources[0x2d]	964	1			T24	1		T96	2		T220	1
valid_sources[0x2e]	1398	1			T92	2		T34	1		T79	1
valid_sources[0x2f]	927	1			T92	1		T94	2		T79	2
valid_sources[0x30]	810	1			T92	2		T87	1		T41	1
valid_sources[0x31]	875	1			T92	1		T79	1		T254	2
valid_sources[0x32]	1034	1			T92	1		T94	2		T34	4
valid_sources[0x33]	1208	1			T92	3		T79	3		T254	2
valid_sources[0x34]	773	1			T5	1		T92	1		T34	2
valid_sources[0x35]	793	1			T81	2		T92	1		T79	1
valid_sources[0x36]	833	1			T20	1		T92	1		T94	5
valid_sources[0x37]	1304	1			T24	3		T16	1		T33	1
valid_sources[0x38]	950	1			T66	1		T92	2		T93	13
valid_sources[0x39]	1051	1			T24	2		T81	1		T92	2
valid_sources[0x3a]	807	1			T5	1		T33	2		T92	3
valid_sources[0x3b]	835	1			T92	1		T221	1		T34	1
valid_sources[0x3c]	1962	1			T81	1		T32	4		T92	4
valid_sources[0x3d]	1266	1			T16	1		T20	1		T34	2
valid_sources[0x3e]	931	1			T81	2		T92	3		T34	1
valid_sources[0x3f]	959	1			T24	1		T8	6		T95	2
valid_sources[0x40]	903	1			T7	1		T92	3		T34	1
valid_sources[0x41]	965	1			T33	3		T92	1		T34	1
valid_sources[0x42]	930	1			T79	1		T41	1		T21	6
valid_sources[0x43]	1038	1			T81	2		T96	3		T92	1
valid_sources[0x44]	1016	1			T36	1		T81	2		T92	1
valid_sources[0x45]	1069	1			T92	1		T87	1		T77	1
valid_sources[0x46]	1473	1			T92	3		T34	1		T74	1
valid_sources[0x47]	904	1			T24	3		T1	2		T92	2
valid_sources[0x48]	977	1			T24	1		T81	1		T92	2
valid_sources[0x49]	1045	1			T92	1		T40	1		T34	4
valid_sources[0x4a]	788	1			T5	1		T81	2		T34	2
valid_sources[0x4b]	825	1			T96	4		T94	1		T222	2
valid_sources[0x4c]	964	1			T24	2		T92	1		T34	1
valid_sources[0x4d]	761	1			T96	17		T92	4		T34	2
valid_sources[0x4e]	838	1			T5	1		T14	3		T36	7
valid_sources[0x4f]	739	1			T92	2		T34	1		T74	1
valid_sources[0x50]	1145	1			T5	1		T92	2		T95	3
valid_sources[0x51]	1045	1			T40	1		T79	4		T41	3
valid_sources[0x52]	879	1			T92	4		T34	1		T74	2
valid_sources[0x53]	1142	1			T24	1		T14	4		T81	2
valid_sources[0x54]	1583	1			T2	2		T96	2		T92	4
valid_sources[0x55]	922	1			T81	3		T92	3		T34	1
valid_sources[0x56]	909	1			T5	2		T24	4		T92	1
valid_sources[0x57]	823	1			T92	2		T34	2		T79	1
valid_sources[0x58]	2112	1			T87	1		T34	1		T55	2
valid_sources[0x59]	946	1			T20	1		T92	2		T94	1
valid_sources[0x5a]	851	1			T5	1		T81	1		T92	1
valid_sources[0x5b]	820	1			T24	1		T92	1		T95	3
valid_sources[0x5c]	985	1			T83	1		T41	4		T207	6
valid_sources[0x5d]	850	1			T33	1		T34	2		T254	2
valid_sources[0x5e]	797	1			T14	1		T19	1		T36	1
valid_sources[0x5f]	1971	1			T94	1		T254	2		T21	1
valid_sources[0x60]	1539	1			T19	1		T20	1		T81	3
valid_sources[0x61]	799	1			T16	1		T19	1		T34	1
valid_sources[0x62]	914	1			T92	3		T95	1		T74	1
valid_sources[0x63]	1030	1			T92	1		T34	2		T79	2
valid_sources[0x64]	1514	1			T81	3		T220	1		T74	1
valid_sources[0x65]	890	1			T5	1		T92	6		T87	1
valid_sources[0x66]	857	1			T92	1		T93	3		T34	2
valid_sources[0x67]	916	1			T96	2		T92	1		T34	3
valid_sources[0x68]	875	1			T24	2		T19	1		T81	2
valid_sources[0x69]	757	1			T3	10		T81	1		T92	3
valid_sources[0x6a]	954	1			T24	1		T16	3		T32	2
valid_sources[0x6b]	763	1			T17	19		T92	1		T8	2
valid_sources[0x6c]	1065	1			T8	3		T87	1		T34	1
valid_sources[0x6d]	1025	1			T5	1		T34	1		T79	1
valid_sources[0x6e]	1067	1			T24	1		T81	1		T91	122
valid_sources[0x6f]	885	1			T92	1		T87	1		T34	1
valid_sources[0x70]	806	1			T24	3		T92	1		T34	1
valid_sources[0x71]	854	1			T24	1		T92	5		T87	1
valid_sources[0x72]	1046	1			T5	1		T2	2		T81	2
valid_sources[0x73]	815	1			T1	1		T34	1		T79	2
valid_sources[0x74]	979	1			T92	1		T34	3		T74	1
valid_sources[0x75]	1253	1			T92	2		T34	2		T79	1
valid_sources[0x76]	958	1			T96	13		T92	2		T34	1
valid_sources[0x77]	1706	1			T92	1		T34	2		T74	2
valid_sources[0x78]	884	1			T24	1		T34	3		T79	2
valid_sources[0x79]	839	1			T92	2		T88	3		T55	1
valid_sources[0x7a]	813	1			T92	3		T74	1		T79	1
valid_sources[0x7b]	903	1			T32	1		T87	1		T34	1
valid_sources[0x7c]	799	1			T24	1		T96	5		T39	4
valid_sources[0x7d]	1373	1			T5	1		T24	2		T32	1
valid_sources[0x7e]	1257	1			T32	1		T74	1		T79	1
valid_sources[0x7f]	775	1			T81	1		T92	1		T87	1
valid_sources[0x80]	894	1			T92	4		T93	3		T67	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61219

1

T4

1

T5

10

T6

2

values[0x0]

all_enables

biggest_size

29987

1

T4

2

T5

5

T6

1

values[0x1]

all_enables

biggest_size

21489

1

T4

1

T5

2

T6

4