Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	977756588	10871	0	0
auto_block_debounce_ctl_rd_A	977756588	2366	0	0
auto_block_out_ctl_rd_A	977756588	3126	0	0
com_det_ctl_0_rd_A	977756588	3740	0	0
com_det_ctl_1_rd_A	977756588	3641	0	0
com_det_ctl_2_rd_A	977756588	3736	0	0
com_det_ctl_3_rd_A	977756588	3567	0	0
com_out_ctl_0_rd_A	977756588	4676	0	0
com_out_ctl_1_rd_A	977756588	4243	0	0
com_out_ctl_2_rd_A	977756588	4540	0	0
com_out_ctl_3_rd_A	977756588	4617	0	0
com_pre_det_ctl_0_rd_A	977756588	1943	0	0
com_pre_det_ctl_1_rd_A	977756588	1831	0	0
com_pre_det_ctl_2_rd_A	977756588	1857	0	0
com_pre_det_ctl_3_rd_A	977756588	1822	0	0
com_pre_sel_ctl_0_rd_A	977756588	4852	0	0
com_pre_sel_ctl_1_rd_A	977756588	4733	0	0
com_pre_sel_ctl_2_rd_A	977756588	4803	0	0
com_pre_sel_ctl_3_rd_A	977756588	4716	0	0
com_sel_ctl_0_rd_A	977756588	4765	0	0
com_sel_ctl_1_rd_A	977756588	4617	0	0
com_sel_ctl_2_rd_A	977756588	5064	0	0
com_sel_ctl_3_rd_A	977756588	4708	0	0
ec_rst_ctl_rd_A	977756588	2826	0	0
intr_enable_rd_A	977756588	2662	0	0
key_intr_ctl_rd_A	977756588	4879	0	0
key_intr_debounce_ctl_rd_A	977756588	1859	0	0
key_invert_ctl_rd_A	977756588	5524	0	0
pin_allowed_ctl_rd_A	977756588	7483	0	0
pin_out_ctl_rd_A	977756588	5206	0	0
pin_out_value_rd_A	977756588	5361	0	0
regwen_rd_A	977756588	2208	0	0
ulp_ac_debounce_ctl_rd_A	977756588	2048	0	0
ulp_ctl_rd_A	977756588	2050	0	0
ulp_lid_debounce_ctl_rd_A	977756588	1978	0	0
ulp_pwrb_debounce_ctl_rd_A	977756588	2201	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	10871	0	0
T33	50016	0	0	0
T37	61553	0	0	0
T38	299330	0	0	0
T39	65674	0	0	0
T61	0	5	0	0
T83	124743	0	0	0
T92	197751	7	0	0
T96	421337	4	0	0
T134	0	10	0	0
T212	82457	0	0	0
T254	0	27	0	0
T257	0	8	0	0
T264	0	8	0	0
T315	0	10	0	0
T327	192997	0	0	0
T344	0	11	0	0
T345	0	4	0	0
T346	208920	0	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	2366	0	0
T21	147792	0	0	0
T61	0	16	0	0
T70	228446	12	0	0
T71	82683	0	0	0
T89	59224	0	0	0
T132	0	10	0	0
T151	0	2	0	0
T253	229943	0	0	0
T254	460880	0	0	0
T255	51013	0	0	0
T256	58258	0	0	0
T257	290673	36	0	0
T319	209088	0	0	0
T326	0	24	0	0
T344	0	42	0	0
T345	0	8	0	0
T347	0	11	0	0
T348	0	9	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	3126	0	0
T21	147792	0	0	0
T61	0	14	0	0
T70	228446	5	0	0
T71	82683	0	0	0
T89	59224	0	0	0
T132	0	10	0	0
T151	0	1	0	0
T253	229943	0	0	0
T254	460880	0	0	0
T255	51013	0	0	0
T256	58258	0	0	0
T257	290673	40	0	0
T319	209088	0	0	0
T326	0	31	0	0
T344	0	31	0	0
T345	0	8	0	0
T347	0	15	0	0
T348	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	3740	0	0
T21	147792	80	0	0
T50	0	69	0	0
T61	325019	17	0	0
T71	82683	0	0	0
T82	0	31	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	18	0	0
T256	58258	0	0	0
T257	290673	51	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	13	0	0
T344	0	28	0	0
T345	0	16	0	0
T347	0	19	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	3641	0	0
T21	147792	47	0	0
T50	0	63	0	0
T61	325019	24	0	0
T71	82683	0	0	0
T82	0	43	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	48	0	0
T256	58258	0	0	0
T257	290673	36	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	24	0	0
T344	0	37	0	0
T345	0	19	0	0
T347	0	11	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	3736	0	0
T21	147792	60	0	0
T50	0	69	0	0
T61	325019	16	0	0
T71	82683	0	0	0
T82	0	33	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	31	0	0
T256	58258	0	0	0
T257	290673	44	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	24	0	0
T344	0	27	0	0
T345	0	3	0	0
T347	0	5	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	3567	0	0
T21	147792	88	0	0
T48	0	27	0	0
T50	0	54	0	0
T61	325019	32	0	0
T71	82683	0	0	0
T82	0	59	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	32	0	0
T256	58258	0	0	0
T257	290673	45	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	15	0	0
T344	0	13	0	0
T345	0	10	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4676	0	0
T21	147792	60	0	0
T50	0	76	0	0
T61	325019	30	0	0
T71	82683	0	0	0
T82	0	49	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	27	0	0
T256	58258	0	0	0
T257	290673	46	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	9	0	0
T344	0	39	0	0
T345	0	2	0	0
T347	0	5	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4243	0	0
T21	147792	54	0	0
T50	0	60	0	0
T61	325019	18	0	0
T71	82683	0	0	0
T82	0	58	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	45	0	0
T256	58258	0	0	0
T257	290673	40	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	21	0	0
T344	0	31	0	0
T345	0	9	0	0
T347	0	5	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4540	0	0
T21	147792	83	0	0
T50	0	79	0	0
T61	325019	25	0	0
T71	82683	0	0	0
T82	0	34	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	25	0	0
T256	58258	0	0	0
T257	290673	51	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	11	0	0
T344	0	37	0	0
T345	0	3	0	0
T347	0	7	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4617	0	0
T21	147792	51	0	0
T50	0	82	0	0
T61	325019	24	0	0
T71	82683	0	0	0
T82	0	24	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	41	0	0
T256	58258	0	0	0
T257	290673	47	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	29	0	0
T344	0	32	0	0
T345	0	3	0	0
T347	0	9	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	1943	0	0
T30	187037	0	0	0
T57	144215	0	0	0
T61	325019	9	0	0
T71	82683	0	0	0
T85	97596	0	0	0
T107	0	22	0	0
T213	19387	0	0	0
T257	290673	33	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	10	0	0
T344	0	18	0	0
T345	0	4	0	0
T347	0	3	0	0
T349	0	20	0	0
T350	0	26	0	0
T351	0	20	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	1831	0	0
T30	187037	0	0	0
T57	144215	0	0	0
T61	325019	21	0	0
T71	82683	0	0	0
T85	97596	0	0	0
T107	0	24	0	0
T213	19387	0	0	0
T257	290673	54	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	26	0	0
T344	0	31	0	0
T345	0	5	0	0
T347	0	2	0	0
T349	0	20	0	0
T350	0	20	0	0
T351	0	10	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	1857	0	0
T30	187037	0	0	0
T57	144215	0	0	0
T61	325019	31	0	0
T71	82683	0	0	0
T85	97596	0	0	0
T107	0	14	0	0
T213	19387	0	0	0
T257	290673	37	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	28	0	0
T344	0	48	0	0
T345	0	3	0	0
T347	0	5	0	0
T349	0	24	0	0
T350	0	28	0	0
T351	0	7	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	1822	0	0
T30	187037	0	0	0
T57	144215	0	0	0
T61	325019	6	0	0
T71	82683	0	0	0
T85	97596	0	0	0
T107	0	18	0	0
T213	19387	0	0	0
T257	290673	30	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	7	0	0
T344	0	22	0	0
T345	0	3	0	0
T347	0	5	0	0
T349	0	33	0	0
T350	0	25	0	0
T351	0	12	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4852	0	0
T21	147792	70	0	0
T50	0	66	0	0
T61	325019	18	0	0
T71	82683	0	0	0
T82	0	50	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	52	0	0
T256	58258	0	0	0
T257	290673	39	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	22	0	0
T344	0	19	0	0
T345	0	20	0	0
T347	0	16	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4733	0	0
T21	147792	72	0	0
T50	0	64	0	0
T61	325019	15	0	0
T71	82683	0	0	0
T82	0	68	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	28	0	0
T256	58258	0	0	0
T257	290673	38	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	32	0	0
T344	0	29	0	0
T345	0	16	0	0
T347	0	11	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4803	0	0
T21	147792	46	0	0
T50	0	69	0	0
T61	325019	12	0	0
T71	82683	0	0	0
T82	0	19	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	53	0	0
T256	58258	0	0	0
T257	290673	36	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	6	0	0
T344	0	37	0	0
T345	0	7	0	0
T347	0	14	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4716	0	0
T21	147792	78	0	0
T50	0	55	0	0
T61	325019	31	0	0
T71	82683	0	0	0
T82	0	54	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	18	0	0
T256	58258	0	0	0
T257	290673	24	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	15	0	0
T344	0	29	0	0
T345	0	21	0	0
T347	0	7	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4765	0	0
T21	147792	70	0	0
T50	0	57	0	0
T61	325019	32	0	0
T71	82683	0	0	0
T82	0	31	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	33	0	0
T256	58258	0	0	0
T257	290673	33	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	7	0	0
T344	0	40	0	0
T345	0	7	0	0
T347	0	21	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4617	0	0
T21	147792	60	0	0
T50	0	71	0	0
T61	325019	11	0	0
T71	82683	0	0	0
T82	0	18	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	40	0	0
T256	58258	0	0	0
T257	290673	11	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	18	0	0
T344	0	34	0	0
T345	0	17	0	0
T347	0	25	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	5064	0	0
T21	147792	47	0	0
T50	0	84	0	0
T61	325019	25	0	0
T71	82683	0	0	0
T82	0	50	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	32	0	0
T256	58258	0	0	0
T257	290673	48	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	14	0	0
T344	0	40	0	0
T345	0	12	0	0
T347	0	19	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4708	0	0
T21	147792	57	0	0
T50	0	71	0	0
T61	325019	16	0	0
T71	82683	0	0	0
T82	0	16	0	0
T85	97596	0	0	0
T89	59224	0	0	0
T99	0	29	0	0
T256	58258	0	0	0
T257	290673	35	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	40	0	0
T344	0	28	0	0
T345	0	13	0	0
T347	0	5	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	2826	0	0
T1	253038	0	0	0
T2	219920	0	0	0
T14	50767	0	0	0
T15	103904	0	0	0
T16	59695	0	0	0
T17	250525	0	0	0
T18	31940	0	0	0
T19	72045	2	0	0
T21	0	27	0	0
T25	95287	1	0	0
T26	203510	0	0	0
T34	0	3	0	0
T61	0	14	0	0
T99	0	6	0	0
T257	0	44	0	0
T344	0	18	0	0
T345	0	13	0	0
T352	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	2662	0	0
T21	147792	0	0	0
T55	115956	32	0	0
T61	0	16	0	0
T70	228446	0	0	0
T89	59224	0	0	0
T252	168410	0	0	0
T253	229943	0	0	0
T254	460880	0	0	0
T255	51013	0	0	0
T256	58258	0	0	0
T257	290673	49	0	0
T326	0	19	0	0
T344	0	37	0	0
T345	0	14	0	0
T347	0	18	0	0
T349	0	28	0	0
T350	0	20	0	0
T353	0	14	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	4879	0	0
T11	77637	0	0	0
T34	843599	108	0	0
T35	203708	0	0	0
T55	0	8	0	0
T56	0	3	0	0
T61	0	26	0	0
T74	841295	0	0	0
T75	551451	0	0	0
T76	48732	0	0	0
T77	15210	0	0	0
T78	103875	0	0	0
T79	169821	0	0	0
T102	485596	0	0	0
T257	0	48	0	0
T326	0	19	0	0
T344	0	40	0	0
T345	0	4	0	0
T347	0	13	0	0
T354	0	1	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	1859	0	0
T30	187037	0	0	0
T57	144215	0	0	0
T61	325019	19	0	0
T71	82683	0	0	0
T85	97596	0	0	0
T107	0	9	0	0
T213	19387	0	0	0
T257	290673	25	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	7	0	0
T344	0	24	0	0
T345	0	4	0	0
T347	0	8	0	0
T349	0	21	0	0
T350	0	19	0	0
T351	0	15	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	5524	0	0
T1	253038	0	0	0
T5	32842	76	0	0
T6	24282	0	0	0
T14	50767	0	0	0
T15	103904	0	0	0
T16	59695	0	0	0
T23	101782	0	0	0
T24	60731	0	0	0
T25	95287	0	0	0
T26	203510	0	0	0
T55	0	70	0	0
T61	0	14	0	0
T77	0	37	0	0
T257	0	32	0	0
T344	0	30	0	0
T345	0	13	0	0
T347	0	10	0	0
T355	0	56	0	0
T356	0	62	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	7483	0	0
T32	104132	0	0	0
T33	50016	0	0	0
T37	61553	0	0	0
T38	299330	0	0	0
T61	0	19	0	0
T66	46824	0	0	0
T81	243850	57	0	0
T91	30682	0	0	0
T92	197751	0	0	0
T96	421337	0	0	0
T135	0	56	0	0
T201	0	81	0	0
T212	82457	0	0	0
T257	0	95	0	0
T317	0	71	0	0
T344	0	35	0	0
T345	0	17	0	0
T347	0	14	0	0
T357	0	74	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	5206	0	0
T32	104132	0	0	0
T33	50016	0	0	0
T37	61553	0	0	0
T38	299330	0	0	0
T61	0	24	0	0
T66	46824	0	0	0
T81	243850	72	0	0
T91	30682	0	0	0
T92	197751	0	0	0
T96	421337	0	0	0
T135	0	57	0	0
T201	0	78	0	0
T212	82457	0	0	0
T257	0	132	0	0
T317	0	44	0	0
T344	0	21	0	0
T347	0	14	0	0
T357	0	77	0	0
T358	0	63	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	5361	0	0
T32	104132	0	0	0
T33	50016	0	0	0
T37	61553	0	0	0
T38	299330	0	0	0
T61	0	19	0	0
T66	46824	0	0	0
T81	243850	61	0	0
T91	30682	0	0	0
T92	197751	0	0	0
T96	421337	0	0	0
T135	0	79	0	0
T201	0	89	0	0
T212	82457	0	0	0
T257	0	92	0	0
T317	0	80	0	0
T344	0	19	0	0
T345	0	15	0	0
T347	0	13	0	0
T357	0	63	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	2208	0	0
T30	187037	0	0	0
T57	144215	0	0	0
T61	325019	25	0	0
T71	82683	0	0	0
T85	97596	0	0	0
T107	0	15	0	0
T213	19387	0	0	0
T257	290673	43	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T319	209088	0	0	0
T326	0	25	0	0
T344	0	30	0	0
T345	0	4	0	0
T347	0	14	0	0
T349	0	22	0	0
T350	0	11	0	0
T351	0	14	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	2048	0	0
T30	187037	0	0	0
T57	144215	0	0	0
T61	325019	16	0	0
T71	82683	0	0	0
T85	97596	0	0	0
T103	0	3	0	0
T213	19387	0	0	0
T257	290673	35	0	0
T261	201305	0	0	0
T262	181129	0	0	0
T318	0	1	0	0
T319	209088	0	0	0
T326	0	27	0	0
T344	0	32	0	0
T345	0	3	0	0
T347	0	11	0	0
T349	0	30	0	0
T359	0	7	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	2050	0	0
T8	122035	0	0	0
T33	50016	3	0	0
T35	0	6	0	0
T39	65674	0	0	0
T40	217255	0	0	0
T61	0	18	0	0
T83	124743	0	0	0
T92	197751	0	0	0
T93	143727	0	0	0
T103	0	3	0	0
T257	0	24	0	0
T326	0	18	0	0
T327	192997	0	0	0
T328	50933	0	0	0
T344	0	36	0	0
T345	0	13	0	0
T346	208920	0	0	0
T347	0	6	0	0
T349	0	37	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	1978	0	0
T8	122035	0	0	0
T33	50016	1	0	0
T35	0	4	0	0
T39	65674	0	0	0
T40	217255	0	0	0
T61	0	23	0	0
T83	124743	0	0	0
T92	197751	0	0	0
T93	143727	0	0	0
T103	0	7	0	0
T257	0	46	0	0
T318	0	3	0	0
T326	0	15	0	0
T327	192997	0	0	0
T328	50933	0	0	0
T344	0	30	0	0
T345	0	16	0	0
T346	208920	0	0	0
T347	0	6	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977756588	2201	0	0
T8	122035	0	0	0
T33	50016	4	0	0
T39	65674	0	0	0
T40	217255	0	0	0
T61	0	13	0	0
T83	124743	0	0	0
T92	197751	0	0	0
T93	143727	0	0	0
T257	0	33	0	0
T318	0	2	0	0
T326	0	44	0	0
T327	192997	0	0	0
T328	50933	0	0	0
T344	0	34	0	0
T345	0	18	0	0
T346	208920	0	0	0
T347	0	13	0	0
T349	0	31	0	0
T350	0	15	0	0