| T506 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1303106973 |
|
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Aug 23 05:19:06 PM UTC 24 |
Aug 23 05:19:14 PM UTC 24 |
2613684890 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.4015564449 |
|
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Aug 23 05:19:11 PM UTC 24 |
Aug 23 05:19:15 PM UTC 24 |
3360134796 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3111263118 |
|
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Aug 23 05:19:09 PM UTC 24 |
Aug 23 05:19:16 PM UTC 24 |
4455529963 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.2065155564 |
|
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Aug 23 05:19:16 PM UTC 24 |
Aug 23 05:19:20 PM UTC 24 |
12150629831 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.3549815902 |
|
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Aug 23 05:19:16 PM UTC 24 |
Aug 23 05:19:21 PM UTC 24 |
2019516958 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2010859065 |
|
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Aug 23 05:16:31 PM UTC 24 |
Aug 23 05:19:22 PM UTC 24 |
68668166332 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.3403345916 |
|
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Aug 23 05:18:57 PM UTC 24 |
Aug 23 05:19:23 PM UTC 24 |
11174112332 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1934781948 |
|
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Aug 23 05:19:14 PM UTC 24 |
Aug 23 05:19:24 PM UTC 24 |
3323645683 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.3244658754 |
|
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Aug 23 05:19:24 PM UTC 24 |
Aug 23 05:19:27 PM UTC 24 |
2601401490 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.231907380 |
|
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Aug 23 05:19:23 PM UTC 24 |
Aug 23 05:19:27 PM UTC 24 |
2132400269 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.1867070784 |
|
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Aug 23 05:19:22 PM UTC 24 |
Aug 23 05:19:27 PM UTC 24 |
2470086183 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3889046285 |
|
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Aug 23 05:19:21 PM UTC 24 |
Aug 23 05:19:27 PM UTC 24 |
2109098482 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.387187906 |
|
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Aug 23 05:19:25 PM UTC 24 |
Aug 23 05:19:28 PM UTC 24 |
2647070526 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.4207938139 |
|
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Aug 23 05:18:06 PM UTC 24 |
Aug 23 05:19:31 PM UTC 24 |
155475669910 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1549312439 |
|
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Aug 23 05:19:28 PM UTC 24 |
Aug 23 05:19:32 PM UTC 24 |
7317199911 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1830506979 |
|
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Aug 23 05:19:28 PM UTC 24 |
Aug 23 05:19:32 PM UTC 24 |
3114882625 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.2842464172 |
|
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Aug 23 05:19:27 PM UTC 24 |
Aug 23 05:19:36 PM UTC 24 |
3317501542 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.1438015476 |
|
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Aug 23 05:19:28 PM UTC 24 |
Aug 23 05:19:36 PM UTC 24 |
2485228613 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.2320840376 |
|
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Aug 23 05:17:13 PM UTC 24 |
Aug 23 05:19:37 PM UTC 24 |
108094061293 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.4179484560 |
|
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Aug 23 05:16:33 PM UTC 24 |
Aug 23 05:19:38 PM UTC 24 |
79481148362 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.1905768556 |
|
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Aug 23 05:19:32 PM UTC 24 |
Aug 23 05:19:38 PM UTC 24 |
6301073167 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1910371864 |
|
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Aug 23 05:16:45 PM UTC 24 |
Aug 23 05:19:39 PM UTC 24 |
71603090624 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.3300795532 |
|
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Aug 23 05:19:37 PM UTC 24 |
Aug 23 05:19:40 PM UTC 24 |
2514537631 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.3124321349 |
|
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Aug 23 05:19:37 PM UTC 24 |
Aug 23 05:19:40 PM UTC 24 |
2141404050 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3436308287 |
|
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Aug 23 05:19:32 PM UTC 24 |
Aug 23 05:19:42 PM UTC 24 |
12518181136 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3993085350 |
|
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Aug 23 05:19:38 PM UTC 24 |
Aug 23 05:19:42 PM UTC 24 |
2205878418 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.1852251295 |
|
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Aug 23 05:15:25 PM UTC 24 |
Aug 23 05:19:42 PM UTC 24 |
125888497944 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2337476155 |
|
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Aug 23 05:17:52 PM UTC 24 |
Aug 23 05:19:42 PM UTC 24 |
46675668067 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1192293173 |
|
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Aug 23 05:19:41 PM UTC 24 |
Aug 23 05:19:43 PM UTC 24 |
2689782600 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.474509325 |
|
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Aug 23 05:19:37 PM UTC 24 |
Aug 23 05:19:44 PM UTC 24 |
2011296313 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2414017045 |
|
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Aug 23 05:19:41 PM UTC 24 |
Aug 23 05:19:44 PM UTC 24 |
3223352126 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.340912567 |
|
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Aug 23 05:19:41 PM UTC 24 |
Aug 23 05:19:45 PM UTC 24 |
3530371390 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.255587279 |
|
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Aug 23 05:19:38 PM UTC 24 |
Aug 23 05:19:46 PM UTC 24 |
2511362933 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2421619037 |
|
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Aug 23 05:19:31 PM UTC 24 |
Aug 23 05:19:47 PM UTC 24 |
23860235246 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.2943679876 |
|
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Aug 23 05:19:43 PM UTC 24 |
Aug 23 05:19:47 PM UTC 24 |
2956252046 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.4110013947 |
|
|
Aug 23 05:15:43 PM UTC 24 |
Aug 23 05:19:47 PM UTC 24 |
368726927968 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.2483641671 |
|
|
Aug 23 05:19:45 PM UTC 24 |
Aug 23 05:19:48 PM UTC 24 |
2036984815 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.1214205894 |
|
|
Aug 23 05:19:48 PM UTC 24 |
Aug 23 05:19:50 PM UTC 24 |
2594783732 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.233782191 |
|
|
Aug 23 05:19:48 PM UTC 24 |
Aug 23 05:19:51 PM UTC 24 |
2624233255 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1340183256 |
|
|
Aug 23 05:19:44 PM UTC 24 |
Aug 23 05:19:52 PM UTC 24 |
11721665079 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.358832644 |
|
|
Aug 23 05:19:43 PM UTC 24 |
Aug 23 05:19:52 PM UTC 24 |
6882026955 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.4182589137 |
|
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Aug 23 05:19:49 PM UTC 24 |
Aug 23 05:19:53 PM UTC 24 |
3282097279 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.2643061608 |
|
|
Aug 23 05:19:46 PM UTC 24 |
Aug 23 05:19:53 PM UTC 24 |
2113996459 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.3672811570 |
|
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Aug 23 05:19:47 PM UTC 24 |
Aug 23 05:19:54 PM UTC 24 |
2088090079 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.2678495152 |
|
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Aug 23 05:19:47 PM UTC 24 |
Aug 23 05:19:54 PM UTC 24 |
2457029469 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3400201912 |
|
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Aug 23 05:19:51 PM UTC 24 |
Aug 23 05:19:55 PM UTC 24 |
3861477813 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.2470395013 |
|
|
Aug 23 05:19:55 PM UTC 24 |
Aug 23 05:19:57 PM UTC 24 |
2037299950 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.1893591246 |
|
|
Aug 23 05:19:52 PM UTC 24 |
Aug 23 05:19:58 PM UTC 24 |
4247615374 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2833250794 |
|
|
Aug 23 05:15:42 PM UTC 24 |
Aug 23 05:19:58 PM UTC 24 |
110873454750 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2655903947 |
|
|
Aug 23 05:19:56 PM UTC 24 |
Aug 23 05:19:58 PM UTC 24 |
2128280730 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.2222904299 |
|
|
Aug 23 05:19:59 PM UTC 24 |
Aug 23 05:20:01 PM UTC 24 |
2336534098 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1202021628 |
|
|
Aug 23 05:19:59 PM UTC 24 |
Aug 23 05:20:02 PM UTC 24 |
2633812279 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3264114269 |
|
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Aug 23 05:19:53 PM UTC 24 |
Aug 23 05:20:04 PM UTC 24 |
7147258037 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3846339251 |
|
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Aug 23 05:19:58 PM UTC 24 |
Aug 23 05:20:05 PM UTC 24 |
2459741081 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.844529026 |
|
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Aug 23 05:20:01 PM UTC 24 |
Aug 23 05:20:05 PM UTC 24 |
3974151824 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.1350914631 |
|
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Aug 23 05:19:59 PM UTC 24 |
Aug 23 05:20:06 PM UTC 24 |
2510224654 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1539417086 |
|
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Aug 23 05:20:03 PM UTC 24 |
Aug 23 05:20:07 PM UTC 24 |
3150092158 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.4266025647 |
|
|
Aug 23 05:21:06 PM UTC 24 |
Aug 23 05:21:11 PM UTC 24 |
2789210592 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.877252072 |
|
|
Aug 23 05:17:53 PM UTC 24 |
Aug 23 05:20:10 PM UTC 24 |
2284160438384 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.498663737 |
|
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Aug 23 05:20:06 PM UTC 24 |
Aug 23 05:20:11 PM UTC 24 |
3209960008 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.370993962 |
|
|
Aug 23 05:20:11 PM UTC 24 |
Aug 23 05:20:14 PM UTC 24 |
2040115159 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.350039734 |
|
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Aug 23 05:20:07 PM UTC 24 |
Aug 23 05:20:16 PM UTC 24 |
2738439925 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3148092398 |
|
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Aug 23 05:19:43 PM UTC 24 |
Aug 23 05:20:16 PM UTC 24 |
27083642937 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.1062929614 |
|
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Aug 23 05:18:52 PM UTC 24 |
Aug 23 05:20:16 PM UTC 24 |
34041688930 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.1417080811 |
|
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Aug 23 05:20:14 PM UTC 24 |
Aug 23 05:20:18 PM UTC 24 |
2479853095 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.3459373013 |
|
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Aug 23 05:20:12 PM UTC 24 |
Aug 23 05:20:19 PM UTC 24 |
2113356712 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.482215698 |
|
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Aug 23 05:20:16 PM UTC 24 |
Aug 23 05:20:19 PM UTC 24 |
2141834813 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.4289579716 |
|
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Aug 23 05:20:10 PM UTC 24 |
Aug 23 05:20:20 PM UTC 24 |
10866793430 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.453070788 |
|
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Aug 23 05:20:18 PM UTC 24 |
Aug 23 05:20:20 PM UTC 24 |
2633474487 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1326734087 |
|
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Aug 23 05:20:05 PM UTC 24 |
Aug 23 05:20:21 PM UTC 24 |
76680306982 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.2375559732 |
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Aug 23 05:20:21 PM UTC 24 |
Aug 23 05:20:23 PM UTC 24 |
5194589721 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2877290680 |
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Aug 23 05:17:29 PM UTC 24 |
Aug 23 05:20:24 PM UTC 24 |
142223519856 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.3393569791 |
|
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Aug 23 05:20:17 PM UTC 24 |
Aug 23 05:20:25 PM UTC 24 |
2509857405 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2373143727 |
|
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Aug 23 05:20:20 PM UTC 24 |
Aug 23 05:20:25 PM UTC 24 |
3501892670 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.633177527 |
|
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Aug 23 05:19:55 PM UTC 24 |
Aug 23 05:20:26 PM UTC 24 |
12995314339 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3315483794 |
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Aug 23 05:20:19 PM UTC 24 |
Aug 23 05:20:26 PM UTC 24 |
2687962156 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.3330688331 |
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Aug 23 05:20:26 PM UTC 24 |
Aug 23 05:20:28 PM UTC 24 |
2078547705 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.4072686411 |
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Aug 23 05:20:20 PM UTC 24 |
Aug 23 05:20:29 PM UTC 24 |
8639738059 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.2913913076 |
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Aug 23 05:20:26 PM UTC 24 |
Aug 23 05:20:29 PM UTC 24 |
2137699668 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.279663922 |
|
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Aug 23 05:20:26 PM UTC 24 |
Aug 23 05:20:29 PM UTC 24 |
2474876960 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.2130852822 |
|
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Aug 23 05:20:27 PM UTC 24 |
Aug 23 05:20:31 PM UTC 24 |
2023745172 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1278442941 |
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Aug 23 05:21:04 PM UTC 24 |
Aug 23 05:21:10 PM UTC 24 |
2076565884 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.346020760 |
|
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Aug 23 05:20:29 PM UTC 24 |
Aug 23 05:20:32 PM UTC 24 |
2626871615 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.626286270 |
|
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Aug 23 05:20:29 PM UTC 24 |
Aug 23 05:20:32 PM UTC 24 |
2532376877 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1651925365 |
|
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Aug 23 05:17:20 PM UTC 24 |
Aug 23 05:20:33 PM UTC 24 |
78940381989 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3795197365 |
|
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Aug 23 05:20:29 PM UTC 24 |
Aug 23 05:20:33 PM UTC 24 |
4176055195 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1754675435 |
|
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Aug 23 05:20:25 PM UTC 24 |
Aug 23 05:20:34 PM UTC 24 |
13266872592 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.377590897 |
|
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Aug 23 05:20:30 PM UTC 24 |
Aug 23 05:20:36 PM UTC 24 |
3802955138 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2527821633 |
|
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Aug 23 05:20:37 PM UTC 24 |
Aug 23 05:20:40 PM UTC 24 |
2135354842 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.949166814 |
|
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Aug 23 05:20:31 PM UTC 24 |
Aug 23 05:20:41 PM UTC 24 |
12976056778 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.4158319968 |
|
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Aug 23 05:20:35 PM UTC 24 |
Aug 23 05:20:41 PM UTC 24 |
2012021853 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2246746904 |
|
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Aug 23 05:20:33 PM UTC 24 |
Aug 23 05:20:42 PM UTC 24 |
5286290602 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.569039705 |
|
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Aug 23 05:20:41 PM UTC 24 |
Aug 23 05:20:44 PM UTC 24 |
2487475413 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3511736435 |
|
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Aug 23 05:20:34 PM UTC 24 |
Aug 23 05:20:44 PM UTC 24 |
6384832227 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.2176039378 |
|
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Aug 23 05:20:42 PM UTC 24 |
Aug 23 05:20:46 PM UTC 24 |
2053868925 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.1266410573 |
|
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Aug 23 05:20:44 PM UTC 24 |
Aug 23 05:20:48 PM UTC 24 |
3252289784 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.808969059 |
|
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Aug 23 05:20:46 PM UTC 24 |
Aug 23 05:20:49 PM UTC 24 |
11559460366 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.3117250674 |
|
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Aug 23 05:20:42 PM UTC 24 |
Aug 23 05:20:50 PM UTC 24 |
2515225729 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.2380542993 |
|
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Aug 23 05:20:43 PM UTC 24 |
Aug 23 05:20:51 PM UTC 24 |
2611891964 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.745076732 |
|
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Aug 23 05:20:50 PM UTC 24 |
Aug 23 05:20:53 PM UTC 24 |
2813544051 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2097499289 |
|
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Aug 23 05:20:45 PM UTC 24 |
Aug 23 05:20:55 PM UTC 24 |
3819879535 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.1696040324 |
|
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Aug 23 05:20:21 PM UTC 24 |
Aug 23 05:20:59 PM UTC 24 |
65647859071 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1594682364 |
|
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Aug 23 05:18:12 PM UTC 24 |
Aug 23 05:21:01 PM UTC 24 |
69554211518 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2502754600 |
|
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Aug 23 05:20:51 PM UTC 24 |
Aug 23 05:21:03 PM UTC 24 |
14474855890 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.363689474 |
|
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Aug 23 05:20:57 PM UTC 24 |
Aug 23 05:21:03 PM UTC 24 |
2015692458 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.1965696287 |
|
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Aug 23 05:21:00 PM UTC 24 |
Aug 23 05:21:04 PM UTC 24 |
2116630718 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.2478753395 |
|
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Aug 23 05:21:02 PM UTC 24 |
Aug 23 05:21:05 PM UTC 24 |
2479827479 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.671074682 |
|
|
Aug 23 05:19:43 PM UTC 24 |
Aug 23 05:21:05 PM UTC 24 |
38207332873 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.2503188933 |
|
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Aug 23 05:19:52 PM UTC 24 |
Aug 23 05:21:07 PM UTC 24 |
919641653179 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2034587084 |
|
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Aug 23 05:21:05 PM UTC 24 |
Aug 23 05:21:08 PM UTC 24 |
2629429599 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2500453292 |
|
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Aug 23 05:21:08 PM UTC 24 |
Aug 23 05:21:10 PM UTC 24 |
6441294622 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.1003222736 |
|
|
Aug 23 05:21:04 PM UTC 24 |
Aug 23 05:21:11 PM UTC 24 |
2509497798 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.1309196316 |
|
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Aug 23 05:21:11 PM UTC 24 |
Aug 23 05:21:15 PM UTC 24 |
3836452903 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1904983282 |
|
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Aug 23 05:21:06 PM UTC 24 |
Aug 23 05:21:15 PM UTC 24 |
3046056550 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1808759077 |
|
|
Aug 23 05:19:14 PM UTC 24 |
Aug 23 05:21:16 PM UTC 24 |
52734529951 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.3744292084 |
|
|
Aug 23 05:21:16 PM UTC 24 |
Aug 23 05:21:19 PM UTC 24 |
2128221918 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.3910066342 |
|
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Aug 23 05:21:17 PM UTC 24 |
Aug 23 05:21:21 PM UTC 24 |
2484629385 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.2242575712 |
|
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Aug 23 05:19:28 PM UTC 24 |
Aug 23 05:21:21 PM UTC 24 |
187389924343 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1504910863 |
|
|
Aug 23 05:20:22 PM UTC 24 |
Aug 23 05:21:21 PM UTC 24 |
24833875430 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.3416166724 |
|
|
Aug 23 05:21:15 PM UTC 24 |
Aug 23 05:21:22 PM UTC 24 |
2012608464 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1185123436 |
|
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Aug 23 05:15:49 PM UTC 24 |
Aug 23 05:21:22 PM UTC 24 |
1892938680570 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.3262427955 |
|
|
Aug 23 05:21:19 PM UTC 24 |
Aug 23 05:21:24 PM UTC 24 |
2123367802 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.408172269 |
|
|
Aug 23 05:22:00 PM UTC 24 |
Aug 23 05:22:27 PM UTC 24 |
11897141383 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2666726924 |
|
|
Aug 23 05:21:22 PM UTC 24 |
Aug 23 05:21:24 PM UTC 24 |
2655352268 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.4089389173 |
|
|
Aug 23 05:21:23 PM UTC 24 |
Aug 23 05:21:26 PM UTC 24 |
2570605050 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.1111526144 |
|
|
Aug 23 05:21:22 PM UTC 24 |
Aug 23 05:21:27 PM UTC 24 |
2519870690 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3198230773 |
|
|
Aug 23 05:21:11 PM UTC 24 |
Aug 23 05:21:27 PM UTC 24 |
5623360513 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2561973647 |
|
|
Aug 23 05:21:23 PM UTC 24 |
Aug 23 05:21:29 PM UTC 24 |
3560006029 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2048614185 |
|
|
Aug 23 05:18:34 PM UTC 24 |
Aug 23 05:21:30 PM UTC 24 |
73301218448 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.3596946445 |
|
|
Aug 23 05:21:25 PM UTC 24 |
Aug 23 05:21:33 PM UTC 24 |
2931092588 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4161603318 |
|
|
Aug 23 05:21:23 PM UTC 24 |
Aug 23 05:21:34 PM UTC 24 |
3814430473 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.4032090961 |
|
|
Aug 23 05:21:29 PM UTC 24 |
Aug 23 05:21:35 PM UTC 24 |
2010123236 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3715472819 |
|
|
Aug 23 05:21:27 PM UTC 24 |
Aug 23 05:21:36 PM UTC 24 |
3075899840 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.1251803915 |
|
|
Aug 23 05:21:30 PM UTC 24 |
Aug 23 05:21:37 PM UTC 24 |
2112477617 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.1229029038 |
|
|
Aug 23 05:21:35 PM UTC 24 |
Aug 23 05:21:37 PM UTC 24 |
2166781222 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1643945071 |
|
|
Aug 23 05:20:33 PM UTC 24 |
Aug 23 05:21:38 PM UTC 24 |
27474963352 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.3316364196 |
|
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Aug 23 05:21:34 PM UTC 24 |
Aug 23 05:21:41 PM UTC 24 |
2481199380 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3545525442 |
|
|
Aug 23 05:21:38 PM UTC 24 |
Aug 23 05:21:42 PM UTC 24 |
4265298959 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.630536065 |
|
|
Aug 23 05:20:50 PM UTC 24 |
Aug 23 05:21:42 PM UTC 24 |
99035782417 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3087837031 |
|
|
Aug 23 05:21:38 PM UTC 24 |
Aug 23 05:21:43 PM UTC 24 |
3746553517 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.3309964677 |
|
|
Aug 23 05:21:36 PM UTC 24 |
Aug 23 05:21:44 PM UTC 24 |
2510519374 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3391697700 |
|
|
Aug 23 05:21:37 PM UTC 24 |
Aug 23 05:21:45 PM UTC 24 |
2608764504 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.1767234251 |
|
|
Aug 23 05:21:28 PM UTC 24 |
Aug 23 05:21:46 PM UTC 24 |
10487920036 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.1906910897 |
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Aug 23 05:20:35 PM UTC 24 |
Aug 23 05:21:47 PM UTC 24 |
130930941115 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.1936303639 |
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|
Aug 23 05:21:46 PM UTC 24 |
Aug 23 05:21:49 PM UTC 24 |
2041755300 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.2952521204 |
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|
Aug 23 05:21:43 PM UTC 24 |
Aug 23 05:21:50 PM UTC 24 |
2625848526 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.3633416210 |
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Aug 23 05:21:50 PM UTC 24 |
Aug 23 05:21:53 PM UTC 24 |
2169848903 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.445615078 |
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Aug 23 05:21:47 PM UTC 24 |
Aug 23 05:21:54 PM UTC 24 |
2110377173 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.3567264524 |
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Aug 23 05:21:51 PM UTC 24 |
Aug 23 05:21:54 PM UTC 24 |
2532833930 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.2940184562 |
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Aug 23 05:21:45 PM UTC 24 |
Aug 23 05:21:55 PM UTC 24 |
14298317823 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3897756692 |
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Aug 23 05:21:44 PM UTC 24 |
Aug 23 05:21:56 PM UTC 24 |
8288953595 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.3677036686 |
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Aug 23 05:21:48 PM UTC 24 |
Aug 23 05:21:56 PM UTC 24 |
2458225324 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.965366754 |
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Aug 23 05:21:09 PM UTC 24 |
Aug 23 05:21:58 PM UTC 24 |
86959476554 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1446569146 |
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Aug 23 05:21:54 PM UTC 24 |
Aug 23 05:21:59 PM UTC 24 |
2620045064 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3718790262 |
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Aug 23 05:21:55 PM UTC 24 |
Aug 23 05:21:59 PM UTC 24 |
2926980340 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.119557486 |
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|
Aug 23 05:21:57 PM UTC 24 |
Aug 23 05:22:02 PM UTC 24 |
2438932354 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.960835437 |
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Aug 23 05:21:54 PM UTC 24 |
Aug 23 05:22:02 PM UTC 24 |
5576390306 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2344042664 |
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|
Aug 23 05:21:11 PM UTC 24 |
Aug 23 05:22:02 PM UTC 24 |
43856035042 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.3422716503 |
|
|
Aug 23 05:21:25 PM UTC 24 |
Aug 23 05:22:04 PM UTC 24 |
107069714370 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3964783925 |
|
|
Aug 23 05:21:55 PM UTC 24 |
Aug 23 05:22:04 PM UTC 24 |
3236983786 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.2723873152 |
|
|
Aug 23 05:22:02 PM UTC 24 |
Aug 23 05:22:05 PM UTC 24 |
2046568620 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.1700665958 |
|
|
Aug 23 05:22:04 PM UTC 24 |
Aug 23 05:22:07 PM UTC 24 |
2469311967 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.3215676 |
|
|
Aug 23 05:22:05 PM UTC 24 |
Aug 23 05:22:08 PM UTC 24 |
2521600113 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1933403153 |
|
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Aug 23 05:22:06 PM UTC 24 |
Aug 23 05:22:08 PM UTC 24 |
2637487889 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.2317767835 |
|
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Aug 23 05:22:02 PM UTC 24 |
Aug 23 05:22:09 PM UTC 24 |
2110041615 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.4034194277 |
|
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Aug 23 05:22:05 PM UTC 24 |
Aug 23 05:22:11 PM UTC 24 |
2016544084 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1487990407 |
|
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Aug 23 05:22:09 PM UTC 24 |
Aug 23 05:22:12 PM UTC 24 |
3204723793 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3425951431 |
|
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Aug 23 05:22:08 PM UTC 24 |
Aug 23 05:22:15 PM UTC 24 |
2593188012 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.363762255 |
|
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Aug 23 05:22:09 PM UTC 24 |
Aug 23 05:22:16 PM UTC 24 |
5367841912 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.2435547815 |
|
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Aug 23 05:17:49 PM UTC 24 |
Aug 23 05:22:16 PM UTC 24 |
114351681774 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.4145263993 |
|
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Aug 23 05:21:57 PM UTC 24 |
Aug 23 05:22:16 PM UTC 24 |
26783760262 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.4289362708 |
|
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Aug 23 05:22:11 PM UTC 24 |
Aug 23 05:22:19 PM UTC 24 |
3708145686 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2917409969 |
|
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Aug 23 05:22:15 PM UTC 24 |
Aug 23 05:22:19 PM UTC 24 |
3354382473 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.1150592133 |
|
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Aug 23 05:22:16 PM UTC 24 |
Aug 23 05:22:19 PM UTC 24 |
2134813433 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2158951950 |
|
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Aug 23 05:20:48 PM UTC 24 |
Aug 23 05:22:20 PM UTC 24 |
150780616677 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.2883949658 |
|
|
Aug 23 05:22:16 PM UTC 24 |
Aug 23 05:22:21 PM UTC 24 |
2017038660 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2001984415 |
|
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Aug 23 05:20:34 PM UTC 24 |
Aug 23 05:22:24 PM UTC 24 |
83692428809 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.173007777 |
|
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Aug 23 05:22:19 PM UTC 24 |
Aug 23 05:22:24 PM UTC 24 |
2513462073 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.2600799194 |
|
|
Aug 23 05:20:53 PM UTC 24 |
Aug 23 05:22:24 PM UTC 24 |
164642922754 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3792236432 |
|
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Aug 23 05:22:21 PM UTC 24 |
Aug 23 05:22:25 PM UTC 24 |
2627316516 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3083151858 |
|
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Aug 23 05:22:21 PM UTC 24 |
Aug 23 05:22:25 PM UTC 24 |
3159766980 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.4029807034 |
|
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Aug 23 05:22:19 PM UTC 24 |
Aug 23 05:22:26 PM UTC 24 |
2118065033 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.3614880373 |
|
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Aug 23 05:21:41 PM UTC 24 |
Aug 23 05:22:27 PM UTC 24 |
66054028412 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1685456573 |
|
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Aug 23 05:22:19 PM UTC 24 |
Aug 23 05:22:28 PM UTC 24 |
2469753125 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.298028136 |
|
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Aug 23 05:22:26 PM UTC 24 |
Aug 23 05:22:28 PM UTC 24 |
4571484347 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.987230514 |
|
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Aug 23 05:20:07 PM UTC 24 |
Aug 23 05:22:30 PM UTC 24 |
122220944245 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.1054342404 |
|
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Aug 23 05:22:28 PM UTC 24 |
Aug 23 05:22:30 PM UTC 24 |
2150568693 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.36506209 |
|
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Aug 23 05:22:28 PM UTC 24 |
Aug 23 05:22:30 PM UTC 24 |
2069948464 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.1663588740 |
|
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Aug 23 05:22:28 PM UTC 24 |
Aug 23 05:22:31 PM UTC 24 |
8599610506 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.2012741677 |
|
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Aug 23 05:22:29 PM UTC 24 |
Aug 23 05:22:32 PM UTC 24 |
2469305027 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.4168733843 |
|
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Aug 23 05:22:30 PM UTC 24 |
Aug 23 05:22:33 PM UTC 24 |
2195740025 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.4229974464 |
|
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Aug 23 05:22:25 PM UTC 24 |
Aug 23 05:22:34 PM UTC 24 |
674220162057 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.853642286 |
|
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Aug 23 05:22:27 PM UTC 24 |
Aug 23 05:22:34 PM UTC 24 |
16212815646 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.149717240 |
|
|
Aug 23 05:22:31 PM UTC 24 |
Aug 23 05:22:39 PM UTC 24 |
2512029809 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.308771315 |
|
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Aug 23 05:22:31 PM UTC 24 |
Aug 23 05:22:39 PM UTC 24 |
2611211729 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1194149211 |
|
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Aug 23 05:22:32 PM UTC 24 |
Aug 23 05:22:41 PM UTC 24 |
3127950614 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.3941043784 |
|
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Aug 23 05:22:35 PM UTC 24 |
Aug 23 05:22:42 PM UTC 24 |
2705455899 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1734350423 |
|
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Aug 23 05:22:33 PM UTC 24 |
Aug 23 05:22:43 PM UTC 24 |
3346667640 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.1388200106 |
|
|
Aug 23 05:16:08 PM UTC 24 |
Aug 23 05:22:44 PM UTC 24 |
164457458333 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.2403587523 |
|
|
Aug 23 05:22:16 PM UTC 24 |
Aug 23 05:22:44 PM UTC 24 |
12284726119 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.2590725273 |
|
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Aug 23 05:22:45 PM UTC 24 |
Aug 23 05:22:48 PM UTC 24 |
2479112189 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.955214335 |
|
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Aug 23 05:22:45 PM UTC 24 |
Aug 23 05:22:48 PM UTC 24 |
2183511332 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3688578628 |
|
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Aug 23 05:21:27 PM UTC 24 |
Aug 23 05:22:49 PM UTC 24 |
79918228074 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.416425907 |
|
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Aug 23 05:22:43 PM UTC 24 |
Aug 23 05:22:49 PM UTC 24 |
2012569268 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.213464560 |
|
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Aug 23 05:22:44 PM UTC 24 |
Aug 23 05:22:50 PM UTC 24 |
2108863237 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1715958115 |
|
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Aug 23 05:22:49 PM UTC 24 |
Aug 23 05:22:52 PM UTC 24 |
3688677595 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3846063931 |
|
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Aug 23 05:19:53 PM UTC 24 |
Aug 23 05:22:52 PM UTC 24 |
152154366223 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2460946737 |
|
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Aug 23 05:19:45 PM UTC 24 |
Aug 23 05:22:52 PM UTC 24 |
169476980599 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.229151119 |
|
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Aug 23 05:22:34 PM UTC 24 |
Aug 23 05:22:52 PM UTC 24 |
65384616346 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1770141724 |
|
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Aug 23 05:22:49 PM UTC 24 |
Aug 23 05:22:53 PM UTC 24 |
2625557531 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1436102550 |
|
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Aug 23 05:21:43 PM UTC 24 |
Aug 23 05:22:53 PM UTC 24 |
127066137734 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.814886057 |
|
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Aug 23 05:22:49 PM UTC 24 |
Aug 23 05:22:54 PM UTC 24 |
2517678256 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1550968367 |
|
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Aug 23 05:22:40 PM UTC 24 |
Aug 23 05:22:55 PM UTC 24 |
5942701521 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.483040226 |
|
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Aug 23 05:22:54 PM UTC 24 |
Aug 23 05:22:57 PM UTC 24 |
2034522679 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.4127607986 |
|
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Aug 23 05:22:54 PM UTC 24 |
Aug 23 05:22:58 PM UTC 24 |
2130274723 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.3594728191 |
|
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Aug 23 05:22:42 PM UTC 24 |
Aug 23 05:22:58 PM UTC 24 |
6433556308 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3970510057 |
|
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Aug 23 05:22:53 PM UTC 24 |
Aug 23 05:22:58 PM UTC 24 |
4425637040 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.989453447 |
|
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Aug 23 05:22:53 PM UTC 24 |
Aug 23 05:22:58 PM UTC 24 |
2600166444 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3463614035 |
|
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Aug 23 05:22:51 PM UTC 24 |
Aug 23 05:22:58 PM UTC 24 |
5795257912 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3514680438 |
|
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Aug 23 05:23:22 PM UTC 24 |
Aug 23 05:23:32 PM UTC 24 |
3840805361 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3603564564 |
|
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Aug 23 05:22:51 PM UTC 24 |
Aug 23 05:22:59 PM UTC 24 |
3340923550 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.1721319962 |
|
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Aug 23 05:22:56 PM UTC 24 |
Aug 23 05:23:00 PM UTC 24 |
2455756725 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3057684707 |
|
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Aug 23 05:22:59 PM UTC 24 |
Aug 23 05:23:01 PM UTC 24 |
2817118534 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2837664671 |
|
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Aug 23 05:22:59 PM UTC 24 |
Aug 23 05:23:01 PM UTC 24 |
3617437836 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.1648756836 |
|
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Aug 23 05:22:59 PM UTC 24 |
Aug 23 05:23:02 PM UTC 24 |
2274325431 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.3103166692 |
|
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Aug 23 05:22:59 PM UTC 24 |
Aug 23 05:23:02 PM UTC 24 |
2538106163 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.2468482835 |
|
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Aug 23 05:22:53 PM UTC 24 |
Aug 23 05:23:03 PM UTC 24 |
13265070323 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3067350944 |
|
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Aug 23 05:23:00 PM UTC 24 |
Aug 23 05:23:03 PM UTC 24 |
3887853919 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.49999855 |
|
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Aug 23 05:22:26 PM UTC 24 |
Aug 23 05:23:06 PM UTC 24 |
134517596421 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.2159064895 |
|
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Aug 23 05:23:04 PM UTC 24 |
Aug 23 05:23:07 PM UTC 24 |
2192695945 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.1393908515 |
|
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Aug 23 05:23:00 PM UTC 24 |
Aug 23 05:23:08 PM UTC 24 |
3257230562 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.2578968836 |
|
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Aug 23 05:23:03 PM UTC 24 |
Aug 23 05:23:09 PM UTC 24 |
2012250453 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.2830538727 |
|
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Aug 23 05:23:03 PM UTC 24 |
Aug 23 05:23:10 PM UTC 24 |
2114254220 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.2761924126 |
|
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Aug 23 05:23:07 PM UTC 24 |
Aug 23 05:23:10 PM UTC 24 |
2532291001 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3327111374 |
|
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Aug 23 05:23:07 PM UTC 24 |
Aug 23 05:23:10 PM UTC 24 |
2634172639 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1624779140 |
|
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Aug 23 05:22:59 PM UTC 24 |
Aug 23 05:23:10 PM UTC 24 |
4083801056 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.865064596 |
|
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Aug 23 05:23:03 PM UTC 24 |
Aug 23 05:23:11 PM UTC 24 |
2468715097 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3890451283 |
|
|
Aug 23 05:23:09 PM UTC 24 |
Aug 23 05:23:13 PM UTC 24 |
3345811950 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.497032285 |
|
|
Aug 23 05:23:02 PM UTC 24 |
Aug 23 05:23:15 PM UTC 24 |
9044197245 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2681194848 |
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|
Aug 23 05:23:10 PM UTC 24 |
Aug 23 05:23:17 PM UTC 24 |
2702098534 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.3560463440 |
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|
Aug 23 05:23:16 PM UTC 24 |
Aug 23 05:23:18 PM UTC 24 |
2077653507 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.1510285740 |
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|
Aug 23 05:23:11 PM UTC 24 |
Aug 23 05:23:19 PM UTC 24 |
2616016208 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.296557385 |
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|
Aug 23 05:23:02 PM UTC 24 |
Aug 23 05:23:21 PM UTC 24 |
7794825057 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3786368503 |
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|
Aug 23 05:23:12 PM UTC 24 |
Aug 23 05:23:21 PM UTC 24 |
19393112183 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2772865686 |
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|
Aug 23 05:23:09 PM UTC 24 |
Aug 23 05:23:22 PM UTC 24 |
4264709522 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.2152290107 |
|
|
Aug 23 05:23:18 PM UTC 24 |
Aug 23 05:23:22 PM UTC 24 |
2115617327 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.1703387337 |
|
|
Aug 23 05:23:20 PM UTC 24 |
Aug 23 05:23:22 PM UTC 24 |
2294645459 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.1796905147 |
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|
Aug 23 05:23:11 PM UTC 24 |
Aug 23 05:23:22 PM UTC 24 |
55434337693 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.2304958041 |
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|
Aug 23 05:23:19 PM UTC 24 |
Aug 23 05:23:23 PM UTC 24 |
2465317162 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1104573682 |
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Aug 23 05:23:23 PM UTC 24 |
Aug 23 05:23:25 PM UTC 24 |
8216714317 ps |