| T633 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3346550541 |
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Aug 23 05:23:22 PM UTC 24 |
Aug 23 05:23:30 PM UTC 24 |
2608518456 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.3878674866 |
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Aug 23 05:23:22 PM UTC 24 |
Aug 23 05:23:30 PM UTC 24 |
2512687332 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.94208672 |
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Aug 23 05:16:48 PM UTC 24 |
Aug 23 05:23:30 PM UTC 24 |
188174142104 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.345974818 |
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Aug 23 05:23:11 PM UTC 24 |
Aug 23 05:23:31 PM UTC 24 |
36505840408 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1975993229 |
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Aug 23 05:23:22 PM UTC 24 |
Aug 23 05:23:32 PM UTC 24 |
3417176853 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.882605047 |
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Aug 23 05:23:31 PM UTC 24 |
Aug 23 05:23:33 PM UTC 24 |
2179203521 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.1742899865 |
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Aug 23 05:23:31 PM UTC 24 |
Aug 23 05:23:34 PM UTC 24 |
2127329992 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1775818762 |
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Aug 23 05:22:39 PM UTC 24 |
Aug 23 05:23:35 PM UTC 24 |
81005989613 ps |
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Aug 23 05:23:24 PM UTC 24 |
Aug 23 05:23:36 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3790672711 |
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Aug 23 05:23:33 PM UTC 24 |
Aug 23 05:23:37 PM UTC 24 |
2167720495 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.2513398989 |
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Aug 23 05:23:34 PM UTC 24 |
Aug 23 05:23:37 PM UTC 24 |
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| T641 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2988463968 |
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Aug 23 05:23:35 PM UTC 24 |
Aug 23 05:23:37 PM UTC 24 |
2635531971 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.3208101558 |
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Aug 23 05:23:32 PM UTC 24 |
Aug 23 05:23:38 PM UTC 24 |
2473182693 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2280831568 |
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Aug 23 05:23:36 PM UTC 24 |
Aug 23 05:23:39 PM UTC 24 |
2997878609 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2771100492 |
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Aug 23 05:23:38 PM UTC 24 |
Aug 23 05:23:40 PM UTC 24 |
4316479151 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.4103127142 |
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Aug 23 05:23:37 PM UTC 24 |
Aug 23 05:23:40 PM UTC 24 |
2975924475 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.1059744559 |
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Aug 23 05:22:52 PM UTC 24 |
Aug 23 05:23:41 PM UTC 24 |
130933940741 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.3206374417 |
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Aug 23 05:23:38 PM UTC 24 |
Aug 23 05:23:41 PM UTC 24 |
4350612291 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.3282734422 |
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Aug 23 05:21:12 PM UTC 24 |
Aug 23 05:23:42 PM UTC 24 |
948177847870 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1215702501 |
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Aug 23 05:23:30 PM UTC 24 |
Aug 23 05:23:43 PM UTC 24 |
4341098851 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.2742541640 |
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Aug 23 05:23:42 PM UTC 24 |
Aug 23 05:23:45 PM UTC 24 |
2483862832 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2887733197 |
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Aug 23 05:23:43 PM UTC 24 |
Aug 23 05:23:46 PM UTC 24 |
2159293059 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.3224283750 |
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Aug 23 05:23:43 PM UTC 24 |
Aug 23 05:23:47 PM UTC 24 |
2538514809 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.3211427820 |
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Aug 23 05:23:41 PM UTC 24 |
Aug 23 05:23:48 PM UTC 24 |
2014177755 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2108971952 |
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Aug 23 05:21:58 PM UTC 24 |
Aug 23 05:23:48 PM UTC 24 |
44268014082 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.3744254390 |
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Aug 23 05:23:42 PM UTC 24 |
Aug 23 05:23:48 PM UTC 24 |
2110668855 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2082797427 |
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Aug 23 05:23:46 PM UTC 24 |
Aug 23 05:23:50 PM UTC 24 |
2626440807 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.557152547 |
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Aug 23 05:23:46 PM UTC 24 |
Aug 23 05:23:50 PM UTC 24 |
2870839817 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.1224725791 |
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Aug 23 05:23:30 PM UTC 24 |
Aug 23 05:23:50 PM UTC 24 |
14203985645 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2909339350 |
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Aug 23 05:23:39 PM UTC 24 |
Aug 23 05:23:51 PM UTC 24 |
4022288068 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.4220941920 |
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Aug 23 05:23:48 PM UTC 24 |
Aug 23 05:23:51 PM UTC 24 |
6256425460 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3782466219 |
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Aug 23 05:23:15 PM UTC 24 |
Aug 23 05:23:52 PM UTC 24 |
17990178361 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.570109053 |
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Aug 23 05:23:47 PM UTC 24 |
Aug 23 05:23:53 PM UTC 24 |
3538931751 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.1734638898 |
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Aug 23 05:23:51 PM UTC 24 |
Aug 23 05:23:53 PM UTC 24 |
10770402536 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.3739501936 |
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Aug 23 05:23:49 PM UTC 24 |
Aug 23 05:23:53 PM UTC 24 |
2779244809 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.3252364275 |
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Aug 23 05:15:21 PM UTC 24 |
Aug 23 05:23:55 PM UTC 24 |
234475448301 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.1074282227 |
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Aug 23 05:23:52 PM UTC 24 |
Aug 23 05:23:55 PM UTC 24 |
2116159842 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1934868679 |
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Aug 23 05:23:54 PM UTC 24 |
Aug 23 05:23:57 PM UTC 24 |
2624507782 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.1789828334 |
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Aug 23 05:23:26 PM UTC 24 |
Aug 23 05:23:58 PM UTC 24 |
24085290981 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.1060572687 |
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Aug 23 05:23:52 PM UTC 24 |
Aug 23 05:23:58 PM UTC 24 |
2014110612 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2197604356 |
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Aug 23 05:23:54 PM UTC 24 |
Aug 23 05:23:59 PM UTC 24 |
2256730728 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1088960191 |
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Aug 23 05:23:56 PM UTC 24 |
Aug 23 05:24:00 PM UTC 24 |
3518978441 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.1340524762 |
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Aug 23 05:23:53 PM UTC 24 |
Aug 23 05:24:00 PM UTC 24 |
2458639332 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.939544665 |
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Aug 23 05:23:54 PM UTC 24 |
Aug 23 05:24:01 PM UTC 24 |
2508899307 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.373137715 |
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Aug 23 05:23:59 PM UTC 24 |
Aug 23 05:24:02 PM UTC 24 |
2766105724 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.4094695767 |
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Aug 23 05:23:51 PM UTC 24 |
Aug 23 05:24:03 PM UTC 24 |
3950123955 ps |
| T162 |
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Aug 23 05:23:58 PM UTC 24 |
Aug 23 05:24:05 PM UTC 24 |
4842909979 ps |
| T666 |
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Aug 23 05:24:02 PM UTC 24 |
Aug 23 05:24:05 PM UTC 24 |
2053336240 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.546780189 |
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Aug 23 05:24:03 PM UTC 24 |
Aug 23 05:24:06 PM UTC 24 |
2138219927 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.2919491304 |
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Aug 23 05:24:04 PM UTC 24 |
Aug 23 05:24:07 PM UTC 24 |
2478513501 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.102971286 |
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Aug 23 05:24:06 PM UTC 24 |
Aug 23 05:24:08 PM UTC 24 |
2121259907 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.518584737 |
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Aug 23 05:24:00 PM UTC 24 |
Aug 23 05:24:08 PM UTC 24 |
9589238392 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2355878361 |
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Aug 23 05:24:08 PM UTC 24 |
Aug 23 05:24:11 PM UTC 24 |
3726468099 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.703187920 |
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Aug 23 05:24:07 PM UTC 24 |
Aug 23 05:24:11 PM UTC 24 |
2621243536 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.3391499844 |
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Aug 23 05:24:01 PM UTC 24 |
Aug 23 05:24:12 PM UTC 24 |
15934630270 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.1047375685 |
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Aug 23 05:24:06 PM UTC 24 |
Aug 23 05:24:13 PM UTC 24 |
2511916707 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3764643687 |
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Aug 23 05:24:09 PM UTC 24 |
Aug 23 05:24:14 PM UTC 24 |
3192012368 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3186881276 |
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Aug 23 05:23:01 PM UTC 24 |
Aug 23 05:24:17 PM UTC 24 |
125876845816 ps |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1114963340 |
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Aug 23 05:24:09 PM UTC 24 |
Aug 23 05:24:17 PM UTC 24 |
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| T676 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3459084908 |
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Aug 23 05:23:51 PM UTC 24 |
Aug 23 05:24:21 PM UTC 24 |
48168128476 ps |
| T116 |
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Aug 23 05:24:12 PM UTC 24 |
Aug 23 05:24:22 PM UTC 24 |
4109867467 ps |
| T224 |
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Aug 23 05:24:14 PM UTC 24 |
Aug 23 05:24:22 PM UTC 24 |
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| T225 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.3483637868 |
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Aug 23 05:24:17 PM UTC 24 |
Aug 23 05:24:24 PM UTC 24 |
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Aug 23 05:24:37 PM UTC 24 |
Aug 23 05:24:41 PM UTC 24 |
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Aug 23 05:24:18 PM UTC 24 |
Aug 23 05:24:25 PM UTC 24 |
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Aug 23 05:23:38 PM UTC 24 |
Aug 23 05:24:27 PM UTC 24 |
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Aug 23 05:24:22 PM UTC 24 |
Aug 23 05:24:29 PM UTC 24 |
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Aug 23 05:24:21 PM UTC 24 |
Aug 23 05:24:29 PM UTC 24 |
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Aug 23 05:24:24 PM UTC 24 |
Aug 23 05:24:29 PM UTC 24 |
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Aug 23 05:24:15 PM UTC 24 |
Aug 23 05:24:30 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.551164751 |
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Aug 23 05:24:23 PM UTC 24 |
Aug 23 05:24:31 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.2812926088 |
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Aug 23 05:24:27 PM UTC 24 |
Aug 23 05:24:34 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.734284925 |
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Aug 23 05:19:52 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2856817937 |
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Aug 23 05:24:25 PM UTC 24 |
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4354548533 ps |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.334556096 |
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Aug 23 05:24:12 PM UTC 24 |
Aug 23 05:24:38 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.2244913084 |
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Aug 23 05:24:31 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.1023273005 |
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Aug 23 05:24:37 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2246928654 |
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Aug 23 05:23:41 PM UTC 24 |
Aug 23 05:28:24 PM UTC 24 |
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Aug 23 05:24:39 PM UTC 24 |
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2192089986 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2911253794 |
|
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Aug 23 05:24:32 PM UTC 24 |
Aug 23 05:24:43 PM UTC 24 |
14868971595 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.698020757 |
|
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Aug 23 05:24:38 PM UTC 24 |
Aug 23 05:24:43 PM UTC 24 |
2480569240 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3537220715 |
|
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Aug 23 05:24:00 PM UTC 24 |
Aug 23 05:24:44 PM UTC 24 |
25336449409 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.1929978879 |
|
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Aug 23 05:24:39 PM UTC 24 |
Aug 23 05:24:45 PM UTC 24 |
2514796245 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.3613405440 |
|
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Aug 23 05:24:31 PM UTC 24 |
Aug 23 05:24:45 PM UTC 24 |
85617946297 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.23196522 |
|
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Aug 23 05:23:39 PM UTC 24 |
Aug 23 05:24:45 PM UTC 24 |
27831463993 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1246296465 |
|
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Aug 23 05:22:34 PM UTC 24 |
Aug 23 05:24:47 PM UTC 24 |
530720202888 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.513542978 |
|
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Aug 23 05:24:40 PM UTC 24 |
Aug 23 05:24:48 PM UTC 24 |
2611779580 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.3701603603 |
|
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Aug 23 05:22:10 PM UTC 24 |
Aug 23 05:24:48 PM UTC 24 |
66630772973 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1997545430 |
|
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Aug 23 05:24:43 PM UTC 24 |
Aug 23 05:24:52 PM UTC 24 |
3055977057 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.121376291 |
|
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Aug 23 05:24:45 PM UTC 24 |
Aug 23 05:24:53 PM UTC 24 |
5481080472 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.2850633720 |
|
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Aug 23 05:24:49 PM UTC 24 |
Aug 23 05:24:54 PM UTC 24 |
2471678374 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.2397374972 |
|
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Aug 23 05:24:36 PM UTC 24 |
Aug 23 05:24:54 PM UTC 24 |
7048362686 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3845617411 |
|
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Aug 23 05:24:44 PM UTC 24 |
Aug 23 05:24:54 PM UTC 24 |
3796234481 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.1588467559 |
|
|
Aug 23 05:24:48 PM UTC 24 |
Aug 23 05:24:55 PM UTC 24 |
2010962876 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2075236640 |
|
|
Aug 23 05:24:49 PM UTC 24 |
Aug 23 05:24:56 PM UTC 24 |
2112881655 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.2098519294 |
|
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Aug 23 05:24:52 PM UTC 24 |
Aug 23 05:24:56 PM UTC 24 |
2070330351 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.180763512 |
|
|
Aug 23 05:17:22 PM UTC 24 |
Aug 23 05:24:57 PM UTC 24 |
196421896134 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2314962371 |
|
|
Aug 23 05:24:54 PM UTC 24 |
Aug 23 05:24:57 PM UTC 24 |
2621815933 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3143202751 |
|
|
Aug 23 05:24:55 PM UTC 24 |
Aug 23 05:24:58 PM UTC 24 |
3946028078 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2939999131 |
|
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Aug 23 05:24:46 PM UTC 24 |
Aug 23 05:24:58 PM UTC 24 |
7995026630 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.4064954755 |
|
|
Aug 23 05:24:54 PM UTC 24 |
Aug 23 05:24:59 PM UTC 24 |
2518562861 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.300492209 |
|
|
Aug 23 05:24:55 PM UTC 24 |
Aug 23 05:25:01 PM UTC 24 |
3985848228 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.1628426853 |
|
|
Aug 23 05:24:45 PM UTC 24 |
Aug 23 05:25:02 PM UTC 24 |
6273598621 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3404815505 |
|
|
Aug 23 05:24:56 PM UTC 24 |
Aug 23 05:25:03 PM UTC 24 |
3053463262 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.2362437544 |
|
|
Aug 23 05:25:02 PM UTC 24 |
Aug 23 05:25:04 PM UTC 24 |
2565602311 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2019115725 |
|
|
Aug 23 05:24:54 PM UTC 24 |
Aug 23 05:25:04 PM UTC 24 |
3482513499 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.1687061517 |
|
|
Aug 23 05:24:59 PM UTC 24 |
Aug 23 05:25:05 PM UTC 24 |
2012751810 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3765330634 |
|
|
Aug 23 05:25:03 PM UTC 24 |
Aug 23 05:25:06 PM UTC 24 |
2154255124 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.3379199063 |
|
|
Aug 23 05:25:00 PM UTC 24 |
Aug 23 05:25:07 PM UTC 24 |
2110333524 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.1200933099 |
|
|
Aug 23 05:23:59 PM UTC 24 |
Aug 23 05:25:07 PM UTC 24 |
165172246981 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.877821709 |
|
|
Aug 23 05:25:04 PM UTC 24 |
Aug 23 05:25:08 PM UTC 24 |
2614602141 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1828629526 |
|
|
Aug 23 05:24:46 PM UTC 24 |
Aug 23 05:25:09 PM UTC 24 |
26350783671 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.469781901 |
|
|
Aug 23 05:23:49 PM UTC 24 |
Aug 23 05:25:09 PM UTC 24 |
134302439859 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1315141815 |
|
|
Aug 23 05:24:59 PM UTC 24 |
Aug 23 05:25:10 PM UTC 24 |
4018531797 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.2748676858 |
|
|
Aug 23 05:25:04 PM UTC 24 |
Aug 23 05:25:11 PM UTC 24 |
2514771118 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.1782552553 |
|
|
Aug 23 05:19:09 PM UTC 24 |
Aug 23 05:25:13 PM UTC 24 |
140722761744 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.1610594747 |
|
|
Aug 23 05:23:00 PM UTC 24 |
Aug 23 05:25:13 PM UTC 24 |
59599928321 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.3166013491 |
|
|
Aug 23 05:24:59 PM UTC 24 |
Aug 23 05:25:15 PM UTC 24 |
68201889038 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.406044268 |
|
|
Aug 23 05:25:12 PM UTC 24 |
Aug 23 05:25:15 PM UTC 24 |
2468818250 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.3071738993 |
|
|
Aug 23 05:25:13 PM UTC 24 |
Aug 23 05:25:16 PM UTC 24 |
2038828522 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.798294918 |
|
|
Aug 23 05:25:12 PM UTC 24 |
Aug 23 05:25:16 PM UTC 24 |
2121873654 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.2585534756 |
|
|
Aug 23 05:25:12 PM UTC 24 |
Aug 23 05:25:16 PM UTC 24 |
2688811174 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1265311377 |
|
|
Aug 23 05:25:12 PM UTC 24 |
Aug 23 05:25:18 PM UTC 24 |
2014284359 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3891166167 |
|
|
Aug 23 05:25:16 PM UTC 24 |
Aug 23 05:25:18 PM UTC 24 |
2676278339 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.1019423651 |
|
|
Aug 23 05:25:14 PM UTC 24 |
Aug 23 05:25:19 PM UTC 24 |
2516807290 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.820516298 |
|
|
Aug 23 05:25:12 PM UTC 24 |
Aug 23 05:25:19 PM UTC 24 |
23398488422 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.414634979 |
|
|
Aug 23 05:25:11 PM UTC 24 |
Aug 23 05:25:20 PM UTC 24 |
3403531112 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3011652810 |
|
|
Aug 23 05:25:11 PM UTC 24 |
Aug 23 05:25:20 PM UTC 24 |
3427067093 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4140436422 |
|
|
Aug 23 05:25:17 PM UTC 24 |
Aug 23 05:25:21 PM UTC 24 |
6117509569 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3101528691 |
|
|
Aug 23 05:18:31 PM UTC 24 |
Aug 23 05:25:21 PM UTC 24 |
326368758651 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.3193369596 |
|
|
Aug 23 05:25:20 PM UTC 24 |
Aug 23 05:25:23 PM UTC 24 |
2034360325 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.1680720628 |
|
|
Aug 23 05:24:56 PM UTC 24 |
Aug 23 05:25:24 PM UTC 24 |
45624448103 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2574951937 |
|
|
Aug 23 05:25:12 PM UTC 24 |
Aug 23 05:25:24 PM UTC 24 |
4714547960 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2090363068 |
|
|
Aug 23 05:24:58 PM UTC 24 |
Aug 23 05:25:24 PM UTC 24 |
41235762594 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.957340203 |
|
|
Aug 23 05:25:22 PM UTC 24 |
Aug 23 05:25:25 PM UTC 24 |
2487419882 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3031426058 |
|
|
Aug 23 05:25:16 PM UTC 24 |
Aug 23 05:25:26 PM UTC 24 |
3228429912 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.3419150788 |
|
|
Aug 23 05:25:22 PM UTC 24 |
Aug 23 05:25:26 PM UTC 24 |
2120254745 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3527920457 |
|
|
Aug 23 05:25:16 PM UTC 24 |
Aug 23 05:25:26 PM UTC 24 |
3414397498 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.418580816 |
|
|
Aug 23 05:25:24 PM UTC 24 |
Aug 23 05:25:27 PM UTC 24 |
2525176941 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1544244925 |
|
|
Aug 23 05:25:25 PM UTC 24 |
Aug 23 05:25:28 PM UTC 24 |
2624892734 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.1479635419 |
|
|
Aug 23 05:25:26 PM UTC 24 |
Aug 23 05:25:28 PM UTC 24 |
4282128130 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.598116795 |
|
|
Aug 23 05:25:26 PM UTC 24 |
Aug 23 05:25:29 PM UTC 24 |
2789616090 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.2183023263 |
|
|
Aug 23 05:25:23 PM UTC 24 |
Aug 23 05:25:29 PM UTC 24 |
2197116449 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3800278689 |
|
|
Aug 23 05:25:19 PM UTC 24 |
Aug 23 05:25:30 PM UTC 24 |
3462105317 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2945329146 |
|
|
Aug 23 05:22:13 PM UTC 24 |
Aug 23 05:25:30 PM UTC 24 |
82498277508 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.2802236771 |
|
|
Aug 23 05:25:19 PM UTC 24 |
Aug 23 05:25:31 PM UTC 24 |
8349325089 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.3386615324 |
|
|
Aug 23 05:25:29 PM UTC 24 |
Aug 23 05:25:32 PM UTC 24 |
2129669184 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3766525920 |
|
|
Aug 23 05:25:29 PM UTC 24 |
Aug 23 05:25:32 PM UTC 24 |
2023471234 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.1724777772 |
|
|
Aug 23 05:25:30 PM UTC 24 |
Aug 23 05:25:33 PM UTC 24 |
2176096409 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.750433054 |
|
|
Aug 23 05:25:25 PM UTC 24 |
Aug 23 05:25:35 PM UTC 24 |
3993204755 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.1026913318 |
|
|
Aug 23 05:25:30 PM UTC 24 |
Aug 23 05:25:35 PM UTC 24 |
2472288642 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.1159035178 |
|
|
Aug 23 05:25:30 PM UTC 24 |
Aug 23 05:25:35 PM UTC 24 |
2522193744 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3287251685 |
|
|
Aug 23 05:25:31 PM UTC 24 |
Aug 23 05:25:37 PM UTC 24 |
2619237114 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2098995002 |
|
|
Aug 23 05:25:25 PM UTC 24 |
Aug 23 05:25:37 PM UTC 24 |
4406300649 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3063663223 |
|
|
Aug 23 05:25:33 PM UTC 24 |
Aug 23 05:25:38 PM UTC 24 |
3233549259 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3727045064 |
|
|
Aug 23 05:25:39 PM UTC 24 |
Aug 23 05:25:42 PM UTC 24 |
2125974559 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3489075976 |
|
|
Aug 23 05:25:33 PM UTC 24 |
Aug 23 05:25:42 PM UTC 24 |
3142376799 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.138009594 |
|
|
Aug 23 05:25:35 PM UTC 24 |
Aug 23 05:25:43 PM UTC 24 |
10143220304 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3834553181 |
|
|
Aug 23 05:22:53 PM UTC 24 |
Aug 23 05:25:43 PM UTC 24 |
302795926593 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2622483287 |
|
|
Aug 23 05:25:27 PM UTC 24 |
Aug 23 05:25:44 PM UTC 24 |
6905293968 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3693805725 |
|
|
Aug 23 05:25:43 PM UTC 24 |
Aug 23 05:25:45 PM UTC 24 |
2492290334 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.4206357004 |
|
|
Aug 23 05:25:36 PM UTC 24 |
Aug 23 05:25:45 PM UTC 24 |
4614864387 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.2439300073 |
|
|
Aug 23 05:25:39 PM UTC 24 |
Aug 23 05:25:45 PM UTC 24 |
2016159971 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.3281854078 |
|
|
Aug 23 05:25:29 PM UTC 24 |
Aug 23 05:25:45 PM UTC 24 |
17334045139 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3132926363 |
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|
Aug 23 05:25:43 PM UTC 24 |
Aug 23 05:25:48 PM UTC 24 |
2519398157 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.4228719620 |
|
|
Aug 23 05:25:45 PM UTC 24 |
Aug 23 05:25:48 PM UTC 24 |
2789474762 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.3570119002 |
|
|
Aug 23 05:25:43 PM UTC 24 |
Aug 23 05:25:49 PM UTC 24 |
2234783818 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2221129760 |
|
|
Aug 23 05:25:46 PM UTC 24 |
Aug 23 05:25:49 PM UTC 24 |
11540381031 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.957071419 |
|
|
Aug 23 05:25:46 PM UTC 24 |
Aug 23 05:25:50 PM UTC 24 |
3471307720 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1937007528 |
|
|
Aug 23 05:25:38 PM UTC 24 |
Aug 23 05:25:51 PM UTC 24 |
9536472065 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.4225281512 |
|
|
Aug 23 05:25:44 PM UTC 24 |
Aug 23 05:25:52 PM UTC 24 |
2613629800 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.1227229294 |
|
|
Aug 23 05:25:50 PM UTC 24 |
Aug 23 05:25:52 PM UTC 24 |
2047141124 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.3574416970 |
|
|
Aug 23 05:25:46 PM UTC 24 |
Aug 23 05:25:53 PM UTC 24 |
3465412341 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.108003038 |
|
|
Aug 23 05:22:26 PM UTC 24 |
Aug 23 05:25:54 PM UTC 24 |
89355390448 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2191168762 |
|
|
Aug 23 05:21:37 PM UTC 24 |
Aug 23 05:25:55 PM UTC 24 |
463124364100 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.3201696211 |
|
|
Aug 23 05:25:51 PM UTC 24 |
Aug 23 05:25:55 PM UTC 24 |
2114350920 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.2162338894 |
|
|
Aug 23 05:25:52 PM UTC 24 |
Aug 23 05:25:55 PM UTC 24 |
2490896466 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.1989718919 |
|
|
Aug 23 05:23:23 PM UTC 24 |
Aug 23 05:25:55 PM UTC 24 |
121932143811 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.4922669 |
|
|
Aug 23 05:25:53 PM UTC 24 |
Aug 23 05:25:56 PM UTC 24 |
2239994750 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1338658254 |
|
|
Aug 23 05:25:54 PM UTC 24 |
Aug 23 05:25:57 PM UTC 24 |
2629349869 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.9208738 |
|
|
Aug 23 05:24:30 PM UTC 24 |
Aug 23 05:26:00 PM UTC 24 |
2730521752743 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2862002676 |
|
|
Aug 23 05:25:55 PM UTC 24 |
Aug 23 05:26:00 PM UTC 24 |
3114643683 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.871287304 |
|
|
Aug 23 05:25:53 PM UTC 24 |
Aug 23 05:26:00 PM UTC 24 |
2510771253 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2039933690 |
|
|
Aug 23 05:25:56 PM UTC 24 |
Aug 23 05:26:03 PM UTC 24 |
5069848979 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1649263992 |
|
|
Aug 23 05:25:55 PM UTC 24 |
Aug 23 05:26:03 PM UTC 24 |
5685893774 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.2676084978 |
|
|
Aug 23 05:26:01 PM UTC 24 |
Aug 23 05:26:04 PM UTC 24 |
2037376069 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.4170044723 |
|
|
Aug 23 05:25:50 PM UTC 24 |
Aug 23 05:26:07 PM UTC 24 |
8620916881 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.1625275381 |
|
|
Aug 23 05:25:50 PM UTC 24 |
Aug 23 05:26:08 PM UTC 24 |
6619025258 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.4032853891 |
|
|
Aug 23 05:25:58 PM UTC 24 |
Aug 23 05:26:14 PM UTC 24 |
11484559050 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.524972791 |
|
|
Aug 23 05:24:46 PM UTC 24 |
Aug 23 05:26:17 PM UTC 24 |
160178396264 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.3193075786 |
|
|
Aug 23 05:25:38 PM UTC 24 |
Aug 23 05:26:23 PM UTC 24 |
17244044468 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1292747719 |
|
|
Aug 23 05:26:13 PM UTC 24 |
Aug 23 05:26:27 PM UTC 24 |
72656423943 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.488562569 |
|
|
Aug 23 05:26:01 PM UTC 24 |
Aug 23 05:26:30 PM UTC 24 |
22587837904 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1312818748 |
|
|
Aug 23 05:25:19 PM UTC 24 |
Aug 23 05:26:30 PM UTC 24 |
110787006266 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1674226781 |
|
|
Aug 23 05:26:18 PM UTC 24 |
Aug 23 05:26:34 PM UTC 24 |
26354859254 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1210043788 |
|
|
Aug 23 05:25:56 PM UTC 24 |
Aug 23 05:26:35 PM UTC 24 |
267305269192 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2925940765 |
|
|
Aug 23 05:26:05 PM UTC 24 |
Aug 23 05:26:35 PM UTC 24 |
35234148545 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.2203441981 |
|
|
Aug 23 05:25:26 PM UTC 24 |
Aug 23 05:26:37 PM UTC 24 |
95396539440 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3584747863 |
|
|
Aug 23 05:25:56 PM UTC 24 |
Aug 23 05:26:40 PM UTC 24 |
69780236813 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.4132676836 |
|
|
Aug 23 05:26:31 PM UTC 24 |
Aug 23 05:26:44 PM UTC 24 |
35077176128 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.683914118 |
|
|
Aug 23 05:26:00 PM UTC 24 |
Aug 23 05:26:45 PM UTC 24 |
37230385100 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.1499864682 |
|
|
Aug 23 05:25:19 PM UTC 24 |
Aug 23 05:26:50 PM UTC 24 |
1221335609482 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2061411440 |
|
|
Aug 23 05:26:38 PM UTC 24 |
Aug 23 05:27:06 PM UTC 24 |
58194093788 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1402196918 |
|
|
Aug 23 05:26:36 PM UTC 24 |
Aug 23 05:27:17 PM UTC 24 |
73529651833 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1703675018 |
|
|
Aug 23 05:26:15 PM UTC 24 |
Aug 23 05:27:24 PM UTC 24 |
105472260442 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1397225646 |
|
|
Aug 23 05:26:08 PM UTC 24 |
Aug 23 05:27:26 PM UTC 24 |
127232429372 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.2446396621 |
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|
Aug 23 05:25:46 PM UTC 24 |
Aug 23 05:27:28 PM UTC 24 |
88452451559 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.572488458 |
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|
Aug 23 05:26:35 PM UTC 24 |
Aug 23 05:27:32 PM UTC 24 |
46304622776 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2707215487 |
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Aug 23 05:27:29 PM UTC 24 |
Aug 23 05:27:39 PM UTC 24 |
26190075087 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1923944880 |
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Aug 23 05:26:41 PM UTC 24 |
Aug 23 05:27:44 PM UTC 24 |
25831500300 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1619818321 |
|
|
Aug 23 05:26:53 PM UTC 24 |
Aug 23 05:27:44 PM UTC 24 |
81745449710 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3067094698 |
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Aug 23 05:26:35 PM UTC 24 |
Aug 23 05:27:46 PM UTC 24 |
108097617009 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.931827215 |
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Aug 23 05:26:45 PM UTC 24 |
Aug 23 05:27:49 PM UTC 24 |
24829846201 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.767606868 |
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Aug 23 05:27:07 PM UTC 24 |
Aug 23 05:27:52 PM UTC 24 |
68283014614 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.327520949 |
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Aug 23 05:27:41 PM UTC 24 |
Aug 23 05:27:59 PM UTC 24 |
27345470047 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2615142194 |
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Aug 23 05:27:45 PM UTC 24 |
Aug 23 05:28:01 PM UTC 24 |
27649494308 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.2316666761 |
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Aug 23 05:25:56 PM UTC 24 |
Aug 23 05:28:02 PM UTC 24 |
111274226261 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2482158658 |
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|
Aug 23 05:27:27 PM UTC 24 |
Aug 23 05:28:04 PM UTC 24 |
56285506065 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4070016234 |
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Aug 23 05:26:05 PM UTC 24 |
Aug 23 05:28:06 PM UTC 24 |
99815839328 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.4026185763 |
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Aug 23 05:25:17 PM UTC 24 |
Aug 23 05:28:27 PM UTC 24 |
88629942461 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2603039401 |
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Aug 23 05:28:05 PM UTC 24 |
Aug 23 05:28:27 PM UTC 24 |
26343762491 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4106575387 |
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Aug 23 05:26:45 PM UTC 24 |
Aug 23 05:28:29 PM UTC 24 |
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| T777 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3997983396 |
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Aug 23 05:27:17 PM UTC 24 |
Aug 23 05:28:35 PM UTC 24 |
67277259479 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.61830220 |
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Aug 23 05:25:12 PM UTC 24 |
Aug 23 05:28:36 PM UTC 24 |
879308109236 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1367189722 |
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Aug 23 05:27:45 PM UTC 24 |
Aug 23 05:28:38 PM UTC 24 |
93647024573 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.632663203 |
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Aug 23 05:22:25 PM UTC 24 |
Aug 23 05:28:40 PM UTC 24 |
315013192074 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2447308084 |
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Aug 23 05:28:06 PM UTC 24 |
Aug 23 05:28:41 PM UTC 24 |
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| T779 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3207419028 |
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Aug 23 05:27:25 PM UTC 24 |
Aug 23 05:28:43 PM UTC 24 |
33986766487 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.52464942 |
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Aug 23 05:28:37 PM UTC 24 |
Aug 23 05:28:49 PM UTC 24 |
61426100813 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3882142997 |
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Aug 23 05:28:02 PM UTC 24 |
Aug 23 05:28:53 PM UTC 24 |
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| T400 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1689868179 |
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Aug 23 05:28:02 PM UTC 24 |
Aug 23 05:28:54 PM UTC 24 |
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| T781 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2559785709 |
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Aug 23 05:28:25 PM UTC 24 |
Aug 23 05:28:55 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3378000448 |
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Aug 23 05:28:39 PM UTC 24 |
Aug 23 05:28:57 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3858813820 |
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Aug 23 05:28:00 PM UTC 24 |
Aug 23 05:29:02 PM UTC 24 |
133609997274 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.947682510 |
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Aug 23 05:26:24 PM UTC 24 |
Aug 23 05:29:05 PM UTC 24 |
128955045269 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1849984292 |
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|
Aug 23 05:24:32 PM UTC 24 |
Aug 23 05:29:17 PM UTC 24 |
116833225230 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2853437632 |
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Aug 23 05:26:54 PM UTC 24 |
Aug 23 05:29:21 PM UTC 24 |
59817778584 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.203427562 |
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|
Aug 23 05:27:50 PM UTC 24 |
Aug 23 05:29:26 PM UTC 24 |
79134150287 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3101564364 |
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Aug 23 05:28:03 PM UTC 24 |
Aug 23 05:29:28 PM UTC 24 |
130999314221 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.2951719517 |
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|
Aug 23 05:24:45 PM UTC 24 |
Aug 23 05:29:30 PM UTC 24 |
115122851942 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.274605978 |
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Aug 23 05:26:03 PM UTC 24 |
Aug 23 05:29:37 PM UTC 24 |
87132132999 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2510291094 |
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Aug 23 05:25:37 PM UTC 24 |
Aug 23 05:29:43 PM UTC 24 |
98029061535 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3083543082 |
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|
Aug 23 05:27:53 PM UTC 24 |
Aug 23 05:29:44 PM UTC 24 |
192841159666 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.390983874 |
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Aug 23 05:28:36 PM UTC 24 |
Aug 23 05:30:00 PM UTC 24 |
67576982889 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.3134126048 |
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Aug 23 05:25:36 PM UTC 24 |
Aug 23 05:30:05 PM UTC 24 |
113502600454 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.4012161278 |
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Aug 23 05:27:46 PM UTC 24 |
Aug 23 05:30:05 PM UTC 24 |
54098763511 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1321472336 |
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Aug 23 05:27:42 PM UTC 24 |
Aug 23 05:30:06 PM UTC 24 |
57619448390 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1387313189 |
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Aug 23 05:28:39 PM UTC 24 |
Aug 23 05:30:11 PM UTC 24 |
162924050555 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.3761790651 |
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|
Aug 23 05:25:12 PM UTC 24 |
Aug 23 05:30:19 PM UTC 24 |
132203070104 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2447021976 |
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Aug 23 05:26:09 PM UTC 24 |
Aug 23 05:30:57 PM UTC 24 |
118670726215 ps |