Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.34	96.34	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	96.34	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.34	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	3	59	95.16

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	3	28	90.32	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1882

1

T31

10

T39

5

T37

18

auto[1]

578

1

T31

2

T39

2

T37

6

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1913

1

T31

12

T37

6

T83

16

auto[1]

547

1

T39

7

T37

18

T40

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1899

1

T31

12

T39

2

T37

20

auto[1]

561

1

T39

5

T37

4

T40

11

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1852

1

T31

12

T39

5

T37

20

auto[1]

608

1

T39

2

T37

4

T40

4

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2226

1

T31

11

T39

7

T37

16

auto[1]

234

1

T31

1

T37

8

T38

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2138

1

T31

9

T39

7

T37

24

auto[1]

322

1

T31

3

T85

1

T86

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2207

1

T31

9

T39

7

T37

14

auto[1]

253

1

T31

3

T37

10

T83

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2277

1

T31

11

T39

7

T37

20

auto[1]

183

1

T31

1

T37

4

T84

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2254

1

T31

10

T39

7

T37

20

auto[1]

206

1

T31

2

T37

4

T85

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1758

1

T31

11

T39

5

T37

20

auto[1]

702

1

T31

1

T39

2

T37

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	3	28	90.32	3
Automatically Generated Cross Bins	31	3	28	90.32	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	697	1			T39	7		T40	21		T41	13
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	68	1			T37	2		T86	4		T288	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	29	1			T263	2		T287	2		T253	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	33	1			T37	2		T279	30		T379	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	57	1			T84	1		T85	1		T367	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	19	1			T85	1		T370	1		T362	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	13	1			T380	9		T381	4		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T382	1		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	142	1			T37	2		T38	3		T263	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	18	1			T38	2		T373	8		T382	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	13	1			T356	1		T352	2		T368	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T363	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	7	1			T37	2		T86	5		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T86	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	14	1			T367	3		T278	2		T365	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T383	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	137	1			T86	6		T112	4		T384	20
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	50	1			T87	26		T253	4		T352	7
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	34	1			T85	1		T100	11		T353	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	4	1			T380	4		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	16	1			T384	7		T365	7		T379	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T352	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	12	1			T100	6		T380	6		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	10	1			T229	1		T257	2		T385	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	4	1			T386	4		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	8	1			T31	2		T384	1		T100	4
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	11	1			T112	1		T372	3		T387	2
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T31	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

94

1

T31

2

T86

5

T107

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

132

1

T31

1

T40

10

T86

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

84

1

T184

4

T263

3

T106

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

105

1

T41

6

T42

14

T112

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

41

1

T98

7

T43

6

T384

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

62

1

T87

13

T112

2

T273

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

40

1

T354

4

T270

2

T351

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

70

1

T299

12

T279

15

T100

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

45

1

T85

1

T119

5

T111

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T40

5

T85

1

T44

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

41

1

T280

3

T253

10

T282

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

53

1

T40

4

T41

6

T98

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T86

6

T184

1

T355

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

51

1

T42

1

T107

2

T350

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T289

1

T388

1

T283

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

118

1

T85

1

T43

7

T279

15

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T37

2

T270

3

T287

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T37

2

T38

1

T119

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T347

3

T349

2

T234

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

43

1

T37

2

T42

4

T289

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

34

1

T351

3

T273

1

T348

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

36

1

T38

4

T354

2

T389

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T39

2

T354

2

T346

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T39

5

T37

2

T367

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T40

2

T44

2

T299

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

19

1

T355

2

T362

1

T390

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T84

1

T354

2

T347

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T42

2

T105

2

T229

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T41

1

T272

2

T391

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T351

1

T116

1

T360

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T280

1

T272

1

T348

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded