Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_key_invert_ctl_cg	100.00	1	100	1	64	64
sysrst_ctrl_key_invert_ctl_cg_(1)	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_key_invert_ctl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_invert_ctl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	48	0	48	100.00
Crosses	44	0	44	100.00

Variables for Group Instance sysrst_ctrl_key_invert_ctl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cfg.vif.ac_present	2	0	2	100.00	100	1	1	2
cfg.vif.bat_disable	2	0	2	100.00	100	1	1	2
cfg.vif.key0_in	2	0	2	100.00	100	1	1	2
cfg.vif.key0_out	2	0	2	100.00	100	1	1	2
cfg.vif.key1_in	2	0	2	100.00	100	1	1	2
cfg.vif.key1_out	2	0	2	100.00	100	1	1	2
cfg.vif.key2_in	2	0	2	100.00	100	1	1	2
cfg.vif.key2_out	2	0	2	100.00	100	1	1	2
cfg.vif.lid_open	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_in	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_out	2	0	2	100.00	100	1	1	2
cfg.vif.z3_wakeup	2	0	2	100.00	100	1	1	2
cp_ac_present	2	0	2	100.00	100	1	1	2
cp_bat_disable	2	0	2	100.00	100	1	1	2
cp_key0_in	2	0	2	100.00	100	1	1	2
cp_key0_out	2	0	2	100.00	100	1	1	2
cp_key1_in	2	0	2	100.00	100	1	1	2
cp_key1_out	2	0	2	100.00	100	1	1	2
cp_key2_in	2	0	2	100.00	100	1	1	2
cp_key2_out	2	0	2	100.00	100	1	1	2
cp_lid_open	2	0	2	100.00	100	1	1	2
cp_pwrb_in	2	0	2	100.00	100	1	1	2
cp_pwrb_out	2	0	2	100.00	100	1	1	2
cp_z3_wakeup	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_key_invert_ctl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key0_inXval	4	0	4	100.00	100	1	1	0
key0_outXval	4	0	4	100.00	100	1	1	0
key1_inXval	4	0	4	100.00	100	1	1	0
key1_outXval	4	0	4	100.00	100	1	1	0
key2_inXval	4	0	4	100.00	100	1	1	0
key2_outXval	4	0	4	100.00	100	1	1	0
pwrb_inXval	4	0	4	100.00	100	1	1	0
pwrb_outXval	4	0	4	100.00	100	1	1	0
ac_presentXval	4	0	4	100.00	100	1	1	0
bat_disableXval	2	0	2	100.00	100	1	1	0
lid_openXval	4	0	4	100.00	100	1	1	0
z3_wakeupXval	2	0	2	100.00	100	1	1	0

---

Group Instance : sysrst_ctrl_key_invert_ctl_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	48	0	48	100.00
Crosses	44	0	44	100.00

Variables for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cfg.vif.ac_present	2	0	2	100.00	100	1	1	2
cfg.vif.bat_disable	2	0	2	100.00	100	1	1	2
cfg.vif.key0_in	2	0	2	100.00	100	1	1	2
cfg.vif.key0_out	2	0	2	100.00	100	1	1	2
cfg.vif.key1_in	2	0	2	100.00	100	1	1	2
cfg.vif.key1_out	2	0	2	100.00	100	1	1	2
cfg.vif.key2_in	2	0	2	100.00	100	1	1	2
cfg.vif.key2_out	2	0	2	100.00	100	1	1	2
cfg.vif.lid_open	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_in	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_out	2	0	2	100.00	100	1	1	2
cfg.vif.z3_wakeup	2	0	2	100.00	100	1	1	2
cp_ac_present	2	0	2	100.00	100	1	1	2
cp_bat_disable	2	0	2	100.00	100	1	1	2
cp_key0_in	2	0	2	100.00	100	1	1	2
cp_key0_out	2	0	2	100.00	100	1	1	2
cp_key1_in	2	0	2	100.00	100	1	1	2
cp_key1_out	2	0	2	100.00	100	1	1	2
cp_key2_in	2	0	2	100.00	100	1	1	2
cp_key2_out	2	0	2	100.00	100	1	1	2
cp_lid_open	2	0	2	100.00	100	1	1	2
cp_pwrb_in	2	0	2	100.00	100	1	1	2
cp_pwrb_out	2	0	2	100.00	100	1	1	2
cp_z3_wakeup	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key0_inXval	4	0	4	100.00	100	1	1	0
key0_outXval	4	0	4	100.00	100	1	1	0
key1_inXval	4	0	4	100.00	100	1	1	0
key1_outXval	4	0	4	100.00	100	1	1	0
key2_inXval	4	0	4	100.00	100	1	1	0
key2_outXval	4	0	4	100.00	100	1	1	0
pwrb_inXval	4	0	4	100.00	100	1	1	0
pwrb_outXval	4	0	4	100.00	100	1	1	0
ac_presentXval	4	0	4	100.00	100	1	1	0
bat_disableXval	2	0	2	100.00	100	1	1	0
lid_openXval	4	0	4	100.00	100	1	1	0
z3_wakeupXval	2	0	2	100.00	100	1	1	0

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

673

1

T4

8

T13

8

T26

9

auto[1]

667

1

T4

12

T13

12

T26

11

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659

1

T4

10

T13

9

T26

12

auto[1]

681

1

T4

10

T13

11

T26

8

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645

1

T4

10

T13

11

T26

12

auto[1]

695

1

T4

10

T13

9

T26

8

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

665

1

T4

14

T13

11

T26

9

auto[1]

675

1

T4

6

T13

9

T26

11

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

632

1

T4

9

T13

11

T26

8

auto[1]

708

1

T4

11

T13

9

T26

12

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

693

1

T4

7

T13

9

T26

12

auto[1]

647

1

T4

13

T13

11

T26

8

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

683

1

T4

10

T13

12

T26

13

auto[1]

657

1

T4

10

T13

8

T26

7

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

664

1

T4

14

T13

12

T26

8

auto[1]

676

1

T4

6

T13

8

T26

12

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

719

1

T4

8

T13

12

T26

11

auto[1]

621

1

T4

12

T13

8

T26

9

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

667

1

T4

8

T13

7

T26

13

auto[1]

673

1

T4

12

T13

13

T26

7

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

705

1

T4

14

T13

12

T26

13

auto[1]

635

1

T4

6

T13

8

T26

7

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

644

1

T4

13

T13

9

T26

12

auto[1]

696

1

T4

7

T13

11

T26

8

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

665

1

T4

11

T13

6

T26

12

auto[1]

675

1

T4

9

T13

14

T26

8

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659

1

T4

10

T13

9

T26

12

auto[1]

681

1

T4

10

T13

11

T26

8

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678

1

T4

10

T13

10

T26

11

auto[1]

662

1

T4

10

T13

10

T26

9

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

684

1

T4

12

T13

6

T26

10

auto[1]

656

1

T4

8

T13

14

T26

10

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

677

1

T4

11

T13

11

T26

12

auto[1]

663

1

T4

9

T13

9

T26

8

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

640

1

T4

9

T13

9

T26

12

auto[1]

700

1

T4

11

T13

11

T26

8

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

681

1

T4

12

T13

12

T26

12

auto[1]

659

1

T4

8

T13

8

T26

8

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

686

1

T4

12

T13

12

T26

9

auto[1]

654

1

T4

8

T13

8

T26

11

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T4

8

T13

12

T26

7

auto[1]

693

1

T4

12

T13

8

T26

13

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657

1

T4

7

T13

13

T26

7

auto[1]

683

1

T4

13

T13

7

T26

13

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

691

1

T4

13

T13

12

T26

13

auto[1]

649

1

T4

7

T13

8

T26

7

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

644

1

T4

13

T13

9

T26

12

auto[1]

696

1

T4

7

T13

11

T26

8

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in

cfg.vif.key0_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

333

1

T4

6

T13

6

T26

7

auto[0]

auto[1]

345

1

T4

4

T13

4

T26

4

auto[1]

auto[0]

312

1

T4

4

T13

5

T26

5

auto[1]

auto[1]

350

1

T4

6

T13

5

T26

4

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out

cfg.vif.key0_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

346

1

T4

9

T13

4

T26

5

auto[0]

auto[1]

338

1

T4

3

T13

2

T26

5

auto[1]

auto[0]

319

1

T4

5

T13

7

T26

4

auto[1]

auto[1]

337

1

T4

3

T13

7

T26

6

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in

cfg.vif.key1_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

321

1

T4

6

T13

7

T26

6

auto[0]

auto[1]

356

1

T4

5

T13

4

T26

6

auto[1]

auto[0]

311

1

T4

3

T13

4

T26

2

auto[1]

auto[1]

352

1

T4

6

T13

5

T26

6

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out

cfg.vif.key1_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

333

1

T4

4

T13

5

T26

8

auto[0]

auto[1]

307

1

T4

5

T13

4

T26

4

auto[1]

auto[0]

360

1

T4

3

T13

4

T26

4

auto[1]

auto[1]

340

1

T4

8

T13

7

T26

4

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in

cfg.vif.key2_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

361

1

T4

5

T13

10

T26

9

auto[0]

auto[1]

320

1

T4

7

T13

2

T26

3

auto[1]

auto[0]

322

1

T4

5

T13

2

T26

4

auto[1]

auto[1]

337

1

T4

3

T13

6

T26

4

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out

cfg.vif.key2_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

354

1

T4

7

T13

10

T26

5

auto[0]

auto[1]

332

1

T4

5

T13

2

T26

4

auto[1]

auto[0]

310

1

T4

7

T13

2

T26

3

auto[1]

auto[1]

344

1

T4

1

T13

6

T26

8

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in

cfg.vif.pwrb_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

325

1

T4

4

T13

4

T26

5

auto[0]

auto[1]

332

1

T4

3

T13

9

T26

2

auto[1]

auto[0]

342

1

T4

4

T13

3

T26

8

auto[1]

auto[1]

341

1

T4

9

T13

4

T26

5

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out

cfg.vif.pwrb_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

361

1

T4

10

T13

6

T26

8

auto[0]

auto[1]

330

1

T4

3

T13

6

T26

5

auto[1]

auto[0]

344

1

T4

4

T13

6

T26

5

auto[1]

auto[1]

305

1

T4

3

T13

2

T26

2

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present

cfg.vif.ac_present

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

327

1

T4

4

T13

1

T26

5

auto[0]

auto[1]

338

1

T4

7

T13

5

T26

7

auto[1]

auto[0]

346

1

T4

4

T13

7

T26

4

auto[1]

auto[1]

329

1

T4

5

T13

7

T26

4

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable

cfg.vif.bat_disable

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

659

1

T4

10

T13

9

T26

12

auto[1]

auto[1]

681

1

T4

10

T13

11

T26

8

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open

cfg.vif.lid_open

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

339

1

T4

4

T13

7

T26

5

auto[0]

auto[1]

308

1

T4

4

T13

5

T26

2

auto[1]

auto[0]

380

1

T4

4

T13

5

T26

6

auto[1]

auto[1]

313

1

T4

8

T13

3

T26

7

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup

cfg.vif.z3_wakeup

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

644

1

T4

13

T13

9

T26

12

auto[1]

auto[1]

696

1

T4

7

T13

11

T26

8

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	21	1			T75	13		T410	8
auto[1]	19	1			T75	7		T410	12

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	20	1			T75	8		T410	12
auto[1]	20	1			T75	12		T410	8

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	17	1			T75	8		T410	9
auto[1]	23	1			T75	12		T410	11

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	17	1			T75	10		T410	7
auto[1]	23	1			T75	10		T410	13

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	17	1			T75	9		T410	8
auto[1]	23	1			T75	11		T410	12

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	26	1			T75	15		T410	11
auto[1]	14	1			T75	5		T410	9

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	18	1			T75	12		T410	6
auto[1]	22	1			T75	8		T410	14

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	20	1			T75	8		T410	12
auto[1]	20	1			T75	12		T410	8

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	15	1			T75	8		T410	7
auto[1]	25	1			T75	12		T410	13

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	22	1			T75	9		T410	13
auto[1]	18	1			T75	11		T410	7

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	20	1			T75	9		T410	11
auto[1]	20	1			T75	11		T410	9

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	23	1			T75	12		T410	11
auto[1]	17	1			T75	8		T410	9

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	28	1			T75	16		T410	12
auto[1]	12	1			T75	4		T410	8

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	20	1			T75	8		T410	12
auto[1]	20	1			T75	12		T410	8

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	29	1			T75	13		T410	16
auto[1]	11	1			T75	7		T410	4

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	17	1			T75	9		T410	8
auto[1]	23	1			T75	11		T410	12

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	20	1			T75	11		T410	9
auto[1]	20	1			T75	9		T410	11

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	21	1			T75	11		T410	10
auto[1]	19	1			T75	9		T410	10

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	16	1			T75	8		T410	8
auto[1]	24	1			T75	12		T410	12

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	24	1			T75	12		T410	12
auto[1]	16	1			T75	8		T410	8

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	23	1			T75	12		T410	11
auto[1]	17	1			T75	8		T410	9

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	22	1			T75	13		T410	9
auto[1]	18	1			T75	7		T410	11

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	18	1			T75	9		T410	9
auto[1]	22	1			T75	11		T410	11

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	23	1			T75	12		T410	11
auto[1]	17	1			T75	8		T410	9

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in	cfg.vif.key0_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	12	1			T75	4		T410	8
auto[0]	auto[1]	17	1			T75	9		T410	8
auto[1]	auto[0]	5	1			T75	4		T410	1
auto[1]	auto[1]	6	1			T75	3		T410	3

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out	cfg.vif.key0_out	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	6	1			T75	3		T410	3
auto[0]	auto[1]	11	1			T75	6		T410	5
auto[1]	auto[0]	11	1			T75	7		T410	4
auto[1]	auto[1]	12	1			T75	4		T410	8

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in	cfg.vif.key1_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	12	1			T75	7		T410	5
auto[0]	auto[1]	8	1			T75	4		T410	4
auto[1]	auto[0]	5	1			T75	2		T410	3
auto[1]	auto[1]	15	1			T75	7		T410	8

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out	cfg.vif.key1_out	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	17	1			T75	10		T410	7
auto[0]	auto[1]	4	1			T75	1		T410	3
auto[1]	auto[0]	9	1			T75	5		T410	4
auto[1]	auto[1]	10	1			T75	4		T410	6

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in	cfg.vif.key2_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	6	1			T75	4		T410	2
auto[0]	auto[1]	10	1			T75	4		T410	6
auto[1]	auto[0]	12	1			T75	8		T410	4
auto[1]	auto[1]	12	1			T75	4		T410	8

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out	cfg.vif.key2_out	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	11	1			T75	4		T410	7
auto[0]	auto[1]	13	1			T75	8		T410	5
auto[1]	auto[0]	9	1			T75	4		T410	5
auto[1]	auto[1]	7	1			T75	4		T410	3

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in	cfg.vif.pwrb_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	11	1			T75	7		T410	4
auto[0]	auto[1]	11	1			T75	6		T410	5
auto[1]	auto[0]	11	1			T75	2		T410	9
auto[1]	auto[1]	7	1			T75	5		T410	2

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out	cfg.vif.pwrb_out	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	8	1			T75	5		T410	3
auto[0]	auto[1]	10	1			T75	4		T410	6
auto[1]	auto[0]	12	1			T75	4		T410	8
auto[1]	auto[1]	10	1			T75	7		T410	3

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present	cfg.vif.ac_present	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	14	1			T75	10		T410	4
auto[0]	auto[1]	14	1			T75	6		T410	8
auto[1]	auto[0]	7	1			T75	3		T410	4
auto[1]	auto[1]	5	1			T75	1		T410	4

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable	cfg.vif.bat_disable	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	20	1			T75	8		T410	12
auto[1]	auto[1]	20	1			T75	12		T410	8

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open	cfg.vif.lid_open	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	12	1			T75	5		T410	7
auto[0]	auto[1]	11	1			T75	7		T410	4
auto[1]	auto[0]	3	1			T75	3		-	-
auto[1]	auto[1]	14	1			T75	5		T410	9

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup	cfg.vif.z3_wakeup	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	23	1			T75	12		T410	11
auto[1]	auto[1]	17	1			T75	8		T410	9

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded