Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620

1

T27

8

T76

10

T63

8

auto[1]

660

1

T27

12

T76

10

T63

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

295

1

T27

4

T76

6

T63

4

from_0to1

295

1

T27

4

T76

6

T63

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

624

1

T27

9

T76

9

T63

8

auto[1]

656

1

T27

11

T76

11

T63

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

627

1

T27

10

T76

12

T63

10

auto[1]

653

1

T27

10

T76

8

T63

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

26

1

T63

1

T79

1

T72

1

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T76

1

T177

1

T295

1

auto[0]

from_1to0

auto[1]

auto[0]

32

1

T76

1

T245

1

T411

1

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T76

1

T63

1

T79

2

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T27

1

T245

1

T274

2

auto[0]

from_0to1

auto[0]

auto[1]

35

1

T27

1

T76

1

T177

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T27

1

T76

1

T79

1

auto[0]

from_0to1

auto[1]

auto[1]

44

1

T76

2

T79

1

T177

2

auto[1]

from_1to0

auto[0]

auto[0]

42

1

T27

1

T76

2

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T27

2

T72

2

T245

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T27

1

T76

1

T79

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T63

1

T79

3

T177

2

auto[1]

from_0to1

auto[0]

auto[0]

31

1

T27

1

T79

2

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

32

1

T63

1

T79

1

T295

1

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T76

2

T63

1

T412

2

auto[1]

from_0to1

auto[1]

auto[1]

39

1

T63

1

T79

1

T72

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

638

1

T27

10

T76

10

T63

15

auto[1]

642

1

T27

10

T76

10

T63

5

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

291

1

T27

7

T76

5

T63

6

from_0to1

297

1

T27

7

T76

4

T63

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T27

8

T76

11

T63

12

auto[1]

632

1

T27

12

T76

9

T63

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

635

1

T27

12

T76

8

T63

11

auto[1]

645

1

T27

8

T76

12

T63

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T27

1

T63

4

T79

2

auto[0]

from_1to0

auto[0]

auto[1]

37

1

T63

1

T72

1

T295

2

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T245

1

T217

1

T274

1

auto[0]

from_1to0

auto[1]

auto[1]

38

1

T27

2

T76

3

T72

2

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T27

2

T177

4

T295

1

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T76

1

T63

3

T79

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T27

1

T76

1

T63

1

auto[0]

from_0to1

auto[1]

auto[1]

26

1

T27

3

T63

2

T72

1

auto[1]

from_1to0

auto[0]

auto[0]

35

1

T27

2

T177

1

T412

1

auto[1]

from_1to0

auto[0]

auto[1]

44

1

T76

1

T177

1

T412

1

auto[1]

from_1to0

auto[1]

auto[0]

34

1

T27

2

T76

1

T177

2

auto[1]

from_1to0

auto[1]

auto[1]

20

1

T63

1

T79

1

T274

1

auto[1]

from_0to1

auto[0]

auto[0]

29

1

T63

1

T177

1

T411

1

auto[1]

from_0to1

auto[0]

auto[1]

37

1

T76

1

T72

1

T295

2

auto[1]

from_0to1

auto[1]

auto[0]

38

1

T27

1

T76

1

T295

2

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T79

1

T245

1

T217

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

621

1

T27

11

T76

9

T63

12

auto[1]

659

1

T27

9

T76

11

T63

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

310

1

T27

3

T76

4

T63

5

from_0to1

322

1

T27

4

T76

4

T63

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

611

1

T27

9

T76

9

T63

8

auto[1]

669

1

T27

11

T76

11

T63

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

637

1

T27

10

T76

10

T63

12

auto[1]

643

1

T27

10

T76

10

T63

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T76

2

T63

1

T295

1

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T27

1

T63

1

T79

2

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T76

1

T63

1

T72

1

auto[0]

from_1to0

auto[1]

auto[1]

46

1

T27

1

T177

1

T295

2

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T27

1

T63

2

T177

1

auto[0]

from_0to1

auto[0]

auto[1]

27

1

T27

1

T76

1

T79

2

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T27

1

T295

1

T245

1

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T177

2

T72

1

T295

1

auto[1]

from_1to0

auto[0]

auto[0]

32

1

T79

1

T177

1

T295

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T79

2

T177

2

T245

1

auto[1]

from_1to0

auto[1]

auto[0]

31

1

T27

1

T79

1

T177

1

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T76

1

T63

2

T72

2

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T27

1

T79

2

T177

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T76

1

T79

1

T177

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T63

3

T79

1

T72

1

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T76

2

T79

1

T72

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616

1

T27

8

T76

10

T63

7

auto[1]

664

1

T27

12

T76

10

T63

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

295

1

T27

5

T76

5

T63

5

from_0to1

300

1

T27

5

T76

4

T63

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

635

1

T27

12

T76

11

T63

8

auto[1]

645

1

T27

8

T76

9

T63

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

590

1

T27

7

T76

10

T63

10

auto[1]

690

1

T27

13

T76

10

T63

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

33

1

T27

2

T63

1

T177

1

auto[0]

from_1to0

auto[0]

auto[1]

50

1

T27

1

T76

1

T72

2

auto[0]

from_1to0

auto[1]

auto[0]

27

1

T76

1

T177

1

T217

1

auto[0]

from_1to0

auto[1]

auto[1]

36

1

T27

2

T79

1

T245

1

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T76

1

T79

2

T177

2

auto[0]

from_0to1

auto[0]

auto[1]

37

1

T27

1

T76

1

T63

1

auto[0]

from_0to1

auto[1]

auto[0]

34

1

T27

1

T177

1

T295

1

auto[0]

from_0to1

auto[1]

auto[1]

27

1

T295

3

T164

1

T413

1

auto[1]

from_1to0

auto[0]

auto[0]

40

1

T76

1

T63

1

T79

1

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T76

1

T79

1

T177

1

auto[1]

from_1to0

auto[1]

auto[0]

34

1

T76

1

T63

3

T79

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T79

1

T177

1

T412

2

auto[1]

from_0to1

auto[0]

auto[0]

31

1

T76

1

T79

2

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T27

1

T63

2

T79

1

auto[1]

from_0to1

auto[1]

auto[0]

38

1

T63

1

T177

1

T72

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T27

2

T76

1

T79

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

632

1

T27

11

T76

11

T63

7

auto[1]

648

1

T27

9

T76

9

T63

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

307

1

T27

5

T76

5

T63

4

from_0to1

307

1

T27

6

T76

5

T63

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

607

1

T27

8

T76

9

T63

9

auto[1]

673

1

T27

12

T76

11

T63

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

639

1

T27

6

T76

10

T63

7

auto[1]

641

1

T27

14

T76

10

T63

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

33

1

T76

1

T79

1

T177

1

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T27

2

T76

2

T63

1

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T76

1

T63

1

T79

2

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T27

2

T63

1

T295

1

auto[0]

from_0to1

auto[0]

auto[0]

32

1

T27

1

T63

1

T177

1

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T79

1

T72

1

T295

1

auto[0]

from_0to1

auto[1]

auto[0]

46

1

T27

1

T76

1

T79

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T27

1

T76

2

T79

2

auto[1]

from_1to0

auto[0]

auto[0]

28

1

T72

2

T295

1

T412

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T79

2

T177

1

T295

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T76

1

T63

1

T177

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T27

1

T177

1

T245

1

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T76

1

T79

1

T295

1

auto[1]

from_0to1

auto[0]

auto[1]

31

1

T27

3

T177

1

T164

1

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T76

1

T63

1

T177

1

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T63

2

T295

1

T245

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

651

1

T27

8

T76

7

T63

12

auto[1]

629

1

T27

12

T76

13

T63

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

292

1

T27

6

T76

3

T63

4

from_0to1

296

1

T27

6

T76

3

T63

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687

1

T27

11

T76

10

T63

15

auto[1]

593

1

T27

9

T76

10

T63

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

632

1

T27

12

T76

9

T63

11

auto[1]

648

1

T27

8

T76

11

T63

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

33

1

T79

1

T177

2

T412

1

auto[0]

from_1to0

auto[0]

auto[1]

35

1

T27

1

T63

1

T295

1

auto[0]

from_1to0

auto[1]

auto[0]

41

1

T27

1

T63

1

T164

2

auto[0]

from_1to0

auto[1]

auto[1]

42

1

T76

1

T177

1

T72

3

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T76

1

T177

1

T295

1

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T27

1

T63

1

T177

1

auto[0]

from_0to1

auto[1]

auto[0]

24

1

T27

1

T177

1

T414

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T27

1

T79

1

T177

1

auto[1]

from_1to0

auto[0]

auto[0]

30

1

T177

1

T245

1

T274

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T27

1

T177

1

T295

3

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T27

3

T76

1

T63

2

auto[1]

from_1to0

auto[1]

auto[1]

33

1

T76

1

T79

1

T177

1

auto[1]

from_0to1

auto[0]

auto[0]

40

1

T27

2

T63

2

T217

1

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T27

1

T76

2

T79

2

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T295

1

T245

2

T274

2

auto[1]

from_0to1

auto[1]

auto[1]

29

1

T79

1

T177

1

T295

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

635

1

T27

11

T76

7

T63

12

auto[1]

645

1

T27

9

T76

13

T63

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

305

1

T27

5

T76

5

T63

5

from_0to1

306

1

T27

5

T76

5

T63

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

613

1

T27

8

T76

13

T63

8

auto[1]

667

1

T27

12

T76

7

T63

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

670

1

T27

8

T76

14

T63

12

auto[1]

610

1

T27

12

T76

6

T63

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T76

1

T295

1

T412

2

auto[0]

from_1to0

auto[0]

auto[1]

44

1

T27

1

T72

2

T412

1

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T76

1

T63

1

T295

1

auto[0]

from_1to0

auto[1]

auto[1]

32

1

T27

1

T63

1

T295

1

auto[0]

from_0to1

auto[0]

auto[0]

32

1

T63

2

T79

1

T177

1

auto[0]

from_0to1

auto[0]

auto[1]

29

1

T76

1

T177

1

T72

1

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T27

1

T274

1

T164

1

auto[0]

from_0to1

auto[1]

auto[1]

47

1

T27

1

T76

1

T63

3

auto[1]

from_1to0

auto[0]

auto[0]

30

1

T76

1

T63

1

T79

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T27

1

T79

1

T177

1

auto[1]

from_1to0

auto[1]

auto[0]

47

1

T27

2

T76

2

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

35

1

T63

1

T177

2

T295

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T27

1

T76

3

T79

1

auto[1]

from_0to1

auto[0]

auto[1]

31

1

T27

1

T72

1

T164

1

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T79

1

T177

1

T217

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T27

1

T79

1

T177

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

617

1

T27

6

T76

7

T63

12

auto[1]

663

1

T27

14

T76

13

T63

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

323

1

T27

5

T76

6

T63

4

from_0to1

320

1

T27

6

T76

5

T63

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T27

11

T76

6

T63

9

auto[1]

633

1

T27

9

T76

14

T63

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623

1

T27

8

T76

8

T63

9

auto[1]

657

1

T27

12

T76

12

T63

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

33

1

T79

2

T177

1

T72

1

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T27

1

T76

1

T63

1

auto[0]

from_1to0

auto[1]

auto[0]

39

1

T76

1

T63

1

T79

2

auto[0]

from_1to0

auto[1]

auto[1]

33

1

T63

1

T295

2

T217

1

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T63

1

T177

1

T295

2

auto[0]

from_0to1

auto[0]

auto[1]

41

1

T27

1

T76

1

T79

1

auto[0]

from_0to1

auto[1]

auto[0]

35

1

T27

1

T72

1

T411

1

auto[0]

from_0to1

auto[1]

auto[1]

35

1

T27

1

T76

1

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T27

2

T177

1

T217

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T27

1

T76

1

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T27

1

T76

1

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T76

2

T79

1

T177

1

auto[1]

from_0to1

auto[0]

auto[0]

44

1

T63

1

T79

1

T72

3

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T27

1

T76

2

T63

1

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T76

1

T79

2

T177

1

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T27

2

T295

1

T411

2