Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	139600	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

110328

1

T4

14

T5

1

T1

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	130284	1			T4	22		T5	2		T1	4
values[0x0]	59585	1			T4	9		T1	6		T13	11
values[0x1]	60059	1			T4	13		T1	4		T13	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	113028	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

136900

1

T4

21

T5

1

T1

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1212	1			T8	1		T10	1		T25	1
valid_sources[0x01]	824	1			T15	1		T88	11		T310	1
valid_sources[0x02]	1715	1			T9	1		T25	1		T88	4
valid_sources[0x03]	726	1			T16	3		T6	1		T72	1
valid_sources[0x04]	1658	1			T76	13		T63	3		T78	1
valid_sources[0x05]	1054	1			T19	4		T24	3		T310	1
valid_sources[0x06]	701	1			T7	3		T177	2		T294	1
valid_sources[0x07]	915	1			T88	7		T156	2		T177	2
valid_sources[0x08]	1706	1			T17	1		T25	1		T88	2
valid_sources[0x09]	730	1			T63	1		T88	10		T310	2
valid_sources[0x0a]	646	1			T78	1		T177	4		T72	9
valid_sources[0x0b]	838	1			T13	1		T17	1		T26	2
valid_sources[0x0c]	1449	1			T25	1		T88	11		T79	1
valid_sources[0x0d]	957	1			T2	1		T19	1		T10	1
valid_sources[0x0e]	963	1			T13	1		T9	1		T77	1
valid_sources[0x0f]	2211	1			T77	1		T310	1		T177	1
valid_sources[0x10]	1106	1			T17	1		T63	4		T206	1
valid_sources[0x11]	913	1			T1	4		T17	1		T9	2
valid_sources[0x12]	902	1			T62	2		T30	1		T322	3
valid_sources[0x13]	1021	1			T17	1		T206	1		T177	1
valid_sources[0x14]	793	1			T17	1		T10	1		T77	1
valid_sources[0x15]	1027	1			T17	1		T10	1		T72	19
valid_sources[0x16]	696	1			T88	12		T310	1		T177	2
valid_sources[0x17]	759	1			T17	1		T202	1		T25	1
valid_sources[0x18]	912	1			T25	1		T75	200		T250	2
valid_sources[0x19]	1215	1			T2	1		T28	1		T79	1
valid_sources[0x1a]	916	1			T13	2		T2	1		T17	2
valid_sources[0x1b]	792	1			T19	1		T9	1		T10	1
valid_sources[0x1c]	1083	1			T2	1		T29	3		T76	22
valid_sources[0x1d]	752	1			T17	1		T19	2		T82	1
valid_sources[0x1e]	789	1			T62	2		T9	1		T78	4
valid_sources[0x1f]	721	1			T66	1		T79	1		T30	1
valid_sources[0x20]	656	1			T19	3		T26	1		T77	1
valid_sources[0x21]	746	1			T19	1		T62	1		T310	1
valid_sources[0x22]	1560	1			T62	1		T7	5		T81	1
valid_sources[0x23]	833	1			T2	1		T19	2		T62	1
valid_sources[0x24]	1399	1			T13	10		T19	1		T54	2
valid_sources[0x25]	1429	1			T8	1		T9	1		T25	1
valid_sources[0x26]	828	1			T310	1		T67	1		T36	1
valid_sources[0x27]	644	1			T19	4		T77	2		T310	1
valid_sources[0x28]	817	1			T77	1		T79	1		T156	1
valid_sources[0x29]	697	1			T1	4		T63	3		T310	1
valid_sources[0x2a]	937	1			T310	1		T36	1		T30	1
valid_sources[0x2b]	1576	1			T1	1		T6	1		T78	1
valid_sources[0x2c]	1206	1			T17	3		T10	1		T63	2
valid_sources[0x2d]	890	1			T9	1		T310	1		T36	3
valid_sources[0x2e]	895	1			T56	1		T30	2		T295	3
valid_sources[0x2f]	1082	1			T9	3		T63	1		T310	2
valid_sources[0x30]	1105	1			T13	1		T19	1		T3	5
valid_sources[0x31]	932	1			T6	1		T26	3		T77	1
valid_sources[0x32]	863	1			T17	1		T26	1		T202	1
valid_sources[0x33]	1070	1			T79	1		T322	1		T250	1
valid_sources[0x34]	849	1			T25	1		T63	1		T88	11
valid_sources[0x35]	725	1			T2	1		T310	1		T58	2
valid_sources[0x36]	1097	1			T19	1		T10	1		T63	1
valid_sources[0x37]	898	1			T9	3		T77	1		T88	6
valid_sources[0x38]	1019	1			T17	1		T310	1		T79	2
valid_sources[0x39]	1174	1			T55	2		T310	2		T30	2
valid_sources[0x3a]	1132	1			T19	2		T62	1		T8	1
valid_sources[0x3b]	740	1			T77	1		T310	1		T79	2
valid_sources[0x3c]	837	1			T6	1		T30	1		T295	2
valid_sources[0x3d]	703	1			T202	3		T88	5		T320	1
valid_sources[0x3e]	812	1			T2	1		T53	1		T55	2
valid_sources[0x3f]	1089	1			T88	20		T310	1		T30	1
valid_sources[0x40]	946	1			T17	1		T63	1		T310	2
valid_sources[0x41]	1230	1			T62	1		T78	1		T30	5
valid_sources[0x42]	872	1			T62	1		T10	1		T30	1
valid_sources[0x43]	750	1			T9	1		T310	1		T30	3
valid_sources[0x44]	813	1			T63	2		T310	2		T30	3
valid_sources[0x45]	1594	1			T13	1		T2	1		T55	1
valid_sources[0x46]	772	1			T88	4		T30	1		T250	1
valid_sources[0x47]	1079	1			T17	1		T206	1		T310	1
valid_sources[0x48]	1019	1			T26	3		T88	6		T79	1
valid_sources[0x49]	850	1			T26	3		T320	1		T46	29
valid_sources[0x4a]	863	1			T63	4		T88	15		T310	1
valid_sources[0x4b]	823	1			T26	3		T88	10		T36	2
valid_sources[0x4c]	1656	1			T19	4		T88	1		T206	1
valid_sources[0x4d]	906	1			T55	3		T72	33		T322	1
valid_sources[0x4e]	875	1			T18	3		T19	1		T77	1
valid_sources[0x4f]	720	1			T62	1		T78	3		T310	4
valid_sources[0x50]	675	1			T28	2		T63	3		T88	7
valid_sources[0x51]	855	1			T77	1		T206	1		T310	1
valid_sources[0x52]	843	1			T25	1		T67	1		T293	1
valid_sources[0x53]	738	1			T2	1		T63	3		T78	1
valid_sources[0x54]	745	1			T17	1		T26	1		T81	2
valid_sources[0x55]	776	1			T15	1		T8	1		T88	4
valid_sources[0x56]	1392	1			T10	1		T53	1		T310	2
valid_sources[0x57]	783	1			T26	1		T88	14		T310	1
valid_sources[0x58]	1046	1			T77	1		T310	1		T30	1
valid_sources[0x59]	818	1			T17	1		T77	1		T310	2
valid_sources[0x5a]	800	1			T77	1		T63	3		T310	1
valid_sources[0x5b]	929	1			T15	1		T17	2		T156	1
valid_sources[0x5c]	1027	1			T2	2		T77	1		T63	1
valid_sources[0x5d]	845	1			T77	1		T63	2		T88	14
valid_sources[0x5e]	906	1			T3	3		T26	2		T78	1
valid_sources[0x5f]	751	1			T15	1		T293	2		T322	3
valid_sources[0x60]	819	1			T2	1		T62	2		T53	1
valid_sources[0x61]	779	1			T62	1		T206	1		T323	2
valid_sources[0x62]	713	1			T310	1		T30	1		T415	1
valid_sources[0x63]	901	1			T81	1		T78	2		T310	2
valid_sources[0x64]	782	1			T177	2		T30	1		T322	2
valid_sources[0x65]	1329	1			T17	1		T19	1		T6	1
valid_sources[0x66]	1037	1			T28	1		T310	4		T320	1
valid_sources[0x67]	727	1			T63	3		T51	69		T88	15
valid_sources[0x68]	1055	1			T17	1		T310	2		T36	1
valid_sources[0x69]	779	1			T310	1		T156	1		T177	2
valid_sources[0x6a]	1045	1			T30	2		T322	1		T250	3
valid_sources[0x6b]	786	1			T2	1		T88	12		T327	4
valid_sources[0x6c]	989	1			T9	2		T77	1		T310	1
valid_sources[0x6d]	857	1			T77	1		T25	1		T310	1
valid_sources[0x6e]	695	1			T18	3		T77	1		T88	6
valid_sources[0x6f]	1116	1			T19	2		T28	1		T88	7
valid_sources[0x70]	725	1			T77	1		T63	2		T156	2
valid_sources[0x71]	791	1			T51	27		T310	1		T67	1
valid_sources[0x72]	1080	1			T77	2		T78	4		T50	11
valid_sources[0x73]	755	1			T2	1		T19	2		T26	1
valid_sources[0x74]	802	1			T19	2		T63	2		T79	1
valid_sources[0x75]	851	1			T310	1		T79	1		T36	1
valid_sources[0x76]	810	1			T2	1		T81	1		T28	1
valid_sources[0x77]	839	1			T62	1		T8	1		T30	1
valid_sources[0x78]	826	1			T26	1		T63	1		T30	1
valid_sources[0x79]	912	1			T17	1		T26	1		T77	2
valid_sources[0x7a]	854	1			T26	1		T9	4		T63	2
valid_sources[0x7b]	1122	1			T27	122		T88	4		T206	1
valid_sources[0x7c]	1232	1			T6	1		T77	1		T30	2
valid_sources[0x7d]	1140	1			T17	1		T77	1		T64	6
valid_sources[0x7e]	761	1			T17	2		T62	1		T77	1
valid_sources[0x7f]	878	1			T2	1		T62	1		T25	1
valid_sources[0x80]	752	1			T62	1		T81	1		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59473

1

T4

8

T5

1

T1

3

values[0x0]

all_enables

biggest_size

29652

1

T4

3

T1

4

T13

5

values[0x1]

all_enables

biggest_size

21203

1

T4

3

T13

2

T2

3