Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	91.67	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block]	91.67	1	100	1	64	64

---

Group Instance : tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	2	12	91.67

Variables for Group Instance tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	1	1	50.00	100	0	0	2
cp_num_cmd_err_bits	4	1	3	75.00	100	1	1	0
cp_num_data_err_bits	4	0	4	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_is_mem

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	266012	0			T4	44		T5	2		T1	14

---

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	1	3	75.00

User Defined Bins for cp_num_cmd_err_bits

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[2]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	265820	1			T4	44		T5	2		T1	14
values[1]	21	1			T306	1		T374	1		T375	1
values[3]	102	1			T304	4		T305	8		T306	2

---

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_data_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	265827	1			T4	44		T5	2		T1	14
values[1]	19	1			T304	2		T305	1		T306	2
values[2]	4	1			T376	1		T377	2		T378	1
values[3]	92	1			T304	3		T305	8		T306	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	265732	1			T4	44		T5	2		T1	14
auto[TlIntgErrCmd]	95	1			T304	2		T305	4		T306	4
auto[TlIntgErrData]	88	1			T304	4		T305	8		T306	3
auto[TlIntgErrBoth]	97	1			T304	4		T305	8		T306	3