Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1030104216 11103 0 0
auto_block_debounce_ctl_rd_A 1030104216 2019 0 0
auto_block_out_ctl_rd_A 1030104216 2824 0 0
com_det_ctl_0_rd_A 1030104216 3844 0 0
com_det_ctl_1_rd_A 1030104216 3888 0 0
com_det_ctl_2_rd_A 1030104216 3609 0 0
com_det_ctl_3_rd_A 1030104216 3651 0 0
com_out_ctl_0_rd_A 1030104216 4300 0 0
com_out_ctl_1_rd_A 1030104216 4410 0 0
com_out_ctl_2_rd_A 1030104216 4321 0 0
com_out_ctl_3_rd_A 1030104216 4257 0 0
com_pre_det_ctl_0_rd_A 1030104216 1571 0 0
com_pre_det_ctl_1_rd_A 1030104216 1537 0 0
com_pre_det_ctl_2_rd_A 1030104216 1763 0 0
com_pre_det_ctl_3_rd_A 1030104216 1647 0 0
com_pre_sel_ctl_0_rd_A 1030104216 4475 0 0
com_pre_sel_ctl_1_rd_A 1030104216 4404 0 0
com_pre_sel_ctl_2_rd_A 1030104216 4582 0 0
com_pre_sel_ctl_3_rd_A 1030104216 4749 0 0
com_sel_ctl_0_rd_A 1030104216 4574 0 0
com_sel_ctl_1_rd_A 1030104216 4664 0 0
com_sel_ctl_2_rd_A 1030104216 4715 0 0
com_sel_ctl_3_rd_A 1030104216 4557 0 0
ec_rst_ctl_rd_A 1030104216 2411 0 0
intr_enable_rd_A 1030104216 2120 0 0
key_intr_ctl_rd_A 1030104216 4585 0 0
key_intr_debounce_ctl_rd_A 1030104216 1881 0 0
key_invert_ctl_rd_A 1030104216 5274 0 0
pin_allowed_ctl_rd_A 1030104216 5637 0 0
pin_out_ctl_rd_A 1030104216 4088 0 0
pin_out_value_rd_A 1030104216 4383 0 0
regwen_rd_A 1030104216 1763 0 0
ulp_ac_debounce_ctl_rd_A 1030104216 1672 0 0
ulp_ctl_rd_A 1030104216 1719 0 0
ulp_lid_debounce_ctl_rd_A 1030104216 1699 0 0
ulp_pwrb_debounce_ctl_rd_A 1030104216 1762 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 11103 0 0
T45 0 5 0 0
T51 295071 8 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 13 0 0
T78 58085 0 0 0
T88 466832 8 0 0
T164 0 4 0 0
T206 193289 0 0 0
T219 0 6 0 0
T250 0 6 0 0
T277 0 10 0 0
T310 307810 3 0 0
T322 0 8 0 0
T323 202487 0 0 0
T324 209167 0 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 2019 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T58 0 9 0 0
T59 0 7 0 0
T61 0 18 0 0
T72 0 15 0 0
T78 58085 0 0 0
T88 466832 39 0 0
T164 0 9 0 0
T206 193289 0 0 0
T219 0 49 0 0
T277 0 10 0 0
T310 307810 7 0 0
T322 0 39 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 2824 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T58 0 7 0 0
T59 0 11 0 0
T61 0 8 0 0
T72 0 22 0 0
T78 58085 0 0 0
T88 466832 35 0 0
T164 0 12 0 0
T206 193289 0 0 0
T219 0 41 0 0
T277 0 30 0 0
T310 307810 13 0 0
T322 0 33 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 3844 0 0
T40 0 67 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 16 0 0
T78 58085 0 0 0
T84 0 41 0 0
T88 466832 39 0 0
T138 0 1 0 0
T164 0 11 0 0
T206 193289 0 0 0
T219 0 48 0 0
T277 0 18 0 0
T310 307810 11 0 0
T322 0 33 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 3888 0 0
T40 0 67 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 13 0 0
T78 58085 0 0 0
T84 0 28 0 0
T88 466832 30 0 0
T138 0 10 0 0
T164 0 7 0 0
T206 193289 0 0 0
T219 0 34 0 0
T277 0 29 0 0
T310 307810 23 0 0
T322 0 47 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 3609 0 0
T40 0 48 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 12 0 0
T78 58085 0 0 0
T84 0 47 0 0
T88 466832 31 0 0
T164 0 10 0 0
T206 193289 0 0 0
T219 0 44 0 0
T277 0 20 0 0
T299 0 54 0 0
T310 307810 21 0 0
T322 0 50 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 3651 0 0
T40 0 40 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 18 0 0
T78 58085 0 0 0
T84 0 45 0 0
T88 466832 43 0 0
T138 0 11 0 0
T206 193289 0 0 0
T219 0 44 0 0
T277 0 25 0 0
T299 0 40 0 0
T310 307810 29 0 0
T322 0 37 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4300 0 0
T40 0 40 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 38 0 0
T78 58085 0 0 0
T84 0 52 0 0
T88 466832 31 0 0
T138 0 18 0 0
T164 0 6 0 0
T206 193289 0 0 0
T219 0 29 0 0
T277 0 18 0 0
T310 307810 16 0 0
T322 0 41 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4410 0 0
T40 0 51 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 8 0 0
T78 58085 0 0 0
T84 0 27 0 0
T88 466832 64 0 0
T138 0 17 0 0
T164 0 7 0 0
T206 193289 0 0 0
T219 0 28 0 0
T277 0 12 0 0
T310 307810 12 0 0
T322 0 30 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4321 0 0
T40 0 36 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 37 0 0
T78 58085 0 0 0
T84 0 28 0 0
T88 466832 32 0 0
T138 0 2 0 0
T164 0 11 0 0
T206 193289 0 0 0
T219 0 34 0 0
T277 0 19 0 0
T310 307810 29 0 0
T322 0 26 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4257 0 0
T40 0 47 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 2 0 0
T78 58085 0 0 0
T84 0 23 0 0
T88 466832 37 0 0
T138 0 13 0 0
T164 0 8 0 0
T206 193289 0 0 0
T219 0 32 0 0
T277 0 15 0 0
T310 307810 16 0 0
T322 0 23 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 1571 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 7 0 0
T78 58085 0 0 0
T88 466832 21 0 0
T138 0 7 0 0
T142 0 37 0 0
T164 0 1 0 0
T206 193289 0 0 0
T219 0 37 0 0
T277 0 24 0 0
T310 307810 8 0 0
T322 0 32 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0
T326 0 21 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 1537 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 6 0 0
T78 58085 0 0 0
T88 466832 15 0 0
T138 0 13 0 0
T142 0 27 0 0
T164 0 15 0 0
T206 193289 0 0 0
T219 0 27 0 0
T277 0 22 0 0
T310 307810 17 0 0
T322 0 33 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0
T326 0 13 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 1763 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 13 0 0
T78 58085 0 0 0
T88 466832 42 0 0
T138 0 19 0 0
T142 0 50 0 0
T164 0 10 0 0
T206 193289 0 0 0
T219 0 31 0 0
T277 0 21 0 0
T310 307810 22 0 0
T322 0 37 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0
T326 0 18 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 1647 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 31 0 0
T78 58085 0 0 0
T88 466832 37 0 0
T138 0 11 0 0
T142 0 52 0 0
T164 0 13 0 0
T206 193289 0 0 0
T219 0 41 0 0
T277 0 21 0 0
T310 307810 6 0 0
T322 0 26 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0
T326 0 12 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4475 0 0
T40 0 52 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 26 0 0
T78 58085 0 0 0
T84 0 41 0 0
T88 466832 18 0 0
T138 0 16 0 0
T164 0 3 0 0
T206 193289 0 0 0
T219 0 40 0 0
T277 0 26 0 0
T310 307810 26 0 0
T322 0 25 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4404 0 0
T40 0 31 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 5 0 0
T78 58085 0 0 0
T84 0 39 0 0
T88 466832 34 0 0
T138 0 19 0 0
T164 0 10 0 0
T206 193289 0 0 0
T219 0 29 0 0
T277 0 20 0 0
T310 307810 20 0 0
T322 0 35 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4582 0 0
T40 0 23 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 13 0 0
T78 58085 0 0 0
T84 0 35 0 0
T88 466832 24 0 0
T138 0 7 0 0
T164 0 5 0 0
T206 193289 0 0 0
T219 0 42 0 0
T277 0 25 0 0
T310 307810 12 0 0
T322 0 25 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4749 0 0
T40 0 66 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 18 0 0
T78 58085 0 0 0
T84 0 42 0 0
T88 466832 44 0 0
T138 0 14 0 0
T164 0 10 0 0
T206 193289 0 0 0
T219 0 30 0 0
T277 0 23 0 0
T310 307810 7 0 0
T322 0 40 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4574 0 0
T40 0 67 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 29 0 0
T78 58085 0 0 0
T84 0 35 0 0
T88 466832 50 0 0
T138 0 7 0 0
T164 0 8 0 0
T206 193289 0 0 0
T219 0 33 0 0
T277 0 15 0 0
T310 307810 20 0 0
T322 0 52 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4664 0 0
T40 0 44 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 24 0 0
T78 58085 0 0 0
T84 0 39 0 0
T88 466832 38 0 0
T138 0 15 0 0
T164 0 11 0 0
T206 193289 0 0 0
T219 0 38 0 0
T277 0 21 0 0
T310 307810 17 0 0
T322 0 23 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4715 0 0
T40 0 54 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 22 0 0
T78 58085 0 0 0
T84 0 41 0 0
T88 466832 44 0 0
T138 0 10 0 0
T164 0 5 0 0
T206 193289 0 0 0
T219 0 37 0 0
T277 0 27 0 0
T310 307810 17 0 0
T322 0 50 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4557 0 0
T40 0 40 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 7 0 0
T78 58085 0 0 0
T84 0 54 0 0
T88 466832 27 0 0
T138 0 10 0 0
T164 0 12 0 0
T206 193289 0 0 0
T219 0 25 0 0
T277 0 25 0 0
T310 307810 15 0 0
T322 0 29 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 2411 0 0
T9 124266 0 0 0
T10 248110 0 0 0
T11 257847 0 0 0
T12 75723 0 0 0
T25 11049 0 0 0
T28 158528 0 0 0
T30 0 2 0 0
T66 298107 1 0 0
T72 0 22 0 0
T76 245997 0 0 0
T77 128155 0 0 0
T88 0 34 0 0
T202 51208 0 0 0
T247 0 3 0 0
T298 0 6 0 0
T310 0 14 0 0
T322 0 38 0 0
T325 0 7 0 0
T327 0 3 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 2120 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 45 0 0
T78 58085 0 0 0
T88 466832 33 0 0
T138 0 3 0 0
T142 0 36 0 0
T164 0 4 0 0
T206 193289 0 0 0
T219 0 42 0 0
T277 0 25 0 0
T310 307810 11 0 0
T322 0 39 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0
T326 0 18 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4585 0 0
T30 0 134 0 0
T46 0 4 0 0
T48 0 2 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 14 0 0
T78 58085 0 0 0
T88 466832 46 0 0
T168 0 2 0 0
T194 0 5 0 0
T206 193289 0 0 0
T219 0 43 0 0
T310 307810 10 0 0
T322 0 46 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 1881 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 22 0 0
T78 58085 0 0 0
T88 466832 45 0 0
T138 0 12 0 0
T142 0 35 0 0
T164 0 11 0 0
T206 193289 0 0 0
T219 0 29 0 0
T277 0 19 0 0
T310 307810 20 0 0
T322 0 34 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0
T326 0 18 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 5274 0 0
T1 20909 0 0 0
T2 44403 0 0 0
T4 67021 68 0 0
T5 105739 0 0 0
T13 30005 0 0 0
T14 50770 0 0 0
T15 65227 0 0 0
T16 26612 0 0 0
T17 96989 0 0 0
T18 107069 0 0 0
T64 0 77 0 0
T70 0 81 0 0
T72 0 85 0 0
T75 0 126 0 0
T88 0 32 0 0
T219 0 32 0 0
T277 0 20 0 0
T310 0 25 0 0
T322 0 24 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 5637 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 52 0 0
T78 58085 0 0 0
T88 466832 33 0 0
T164 0 25 0 0
T177 0 78 0 0
T206 193289 0 0 0
T217 0 68 0 0
T219 0 57 0 0
T277 0 13 0 0
T295 0 60 0 0
T310 307810 13 0 0
T322 0 41 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4088 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 91 0 0
T78 58085 0 0 0
T88 466832 36 0 0
T164 0 55 0 0
T177 0 72 0 0
T206 193289 0 0 0
T217 0 60 0 0
T219 0 27 0 0
T277 0 15 0 0
T295 0 79 0 0
T310 307810 21 0 0
T322 0 40 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 4383 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 50 0 0
T78 58085 0 0 0
T88 466832 52 0 0
T164 0 48 0 0
T177 0 65 0 0
T206 193289 0 0 0
T217 0 75 0 0
T219 0 34 0 0
T277 0 20 0 0
T295 0 64 0 0
T310 307810 9 0 0
T322 0 43 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 1763 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 20 0 0
T78 58085 0 0 0
T88 466832 65 0 0
T138 0 11 0 0
T142 0 32 0 0
T164 0 14 0 0
T206 193289 0 0 0
T219 0 52 0 0
T277 0 22 0 0
T310 307810 14 0 0
T322 0 42 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0
T326 0 23 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 1672 0 0
T48 0 4 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 14 0 0
T78 58085 0 0 0
T88 466832 33 0 0
T124 0 4 0 0
T138 0 7 0 0
T164 0 10 0 0
T206 193289 0 0 0
T219 0 52 0 0
T277 0 12 0 0
T310 307810 17 0 0
T322 0 44 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 1719 0 0
T48 0 5 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 27 0 0
T78 58085 0 0 0
T88 466832 38 0 0
T124 0 1 0 0
T138 0 16 0 0
T164 0 2 0 0
T206 193289 0 0 0
T219 0 41 0 0
T277 0 4 0 0
T310 307810 16 0 0
T322 0 29 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 1699 0 0
T48 0 2 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 19 0 0
T78 58085 0 0 0
T88 466832 34 0 0
T124 0 1 0 0
T138 0 2 0 0
T164 0 14 0 0
T206 193289 0 0 0
T219 0 23 0 0
T277 0 23 0 0
T310 307810 10 0 0
T322 0 41 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030104216 1762 0 0
T48 0 9 0 0
T54 106463 0 0 0
T55 21107 0 0 0
T56 233566 0 0 0
T72 0 25 0 0
T78 58085 0 0 0
T88 466832 43 0 0
T124 0 1 0 0
T138 0 3 0 0
T164 0 2 0 0
T206 193289 0 0 0
T219 0 30 0 0
T277 0 10 0 0
T310 307810 23 0 0
T322 0 63 0 0
T323 202487 0 0 0
T324 209167 0 0 0
T325 162827 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%