Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_auto_blk_out_ctl_cg	100.00	1	100	1	64	64
sysrst_ctrl_auto_blk_out_ctl_cg_(1)	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	12	0	12	100.00

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	0	2	100.00	100	1	1	2
cp_key0_out_value	2	0	2	100.00	100	1	1	2
cp_key1_out_sel	2	0	2	100.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	0	2	100.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key1_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key2_out_sel_value	4	0	4	100.00	100	1	1	0

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	12	0	12	100.00

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	0	2	100.00	100	1	1	2
cp_key0_out_value	2	0	2	100.00	100	1	1	2
cp_key1_out_sel	2	0	2	100.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	0	2	100.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key1_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key2_out_sel_value	4	0	4	100.00	100	1	1	0

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98

1

T28

1

T30

1

T66

2

auto[1]

98

1

T28

2

T29

3

T30

2

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91

1

T28

2

T30

2

T66

2

auto[1]

105

1

T28

1

T29

3

T30

1

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93

1

T28

2

T29

2

T66

2

auto[1]

103

1

T28

1

T29

1

T30

3

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93

1

T28

2

T29

1

T30

2

auto[1]

103

1

T28

1

T29

2

T30

1

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102

1

T28

3

T29

2

T30

1

auto[1]

94

1

T29

1

T30

2

T66

1

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97

1

T28

2

T29

2

T30

1

auto[1]

99

1

T28

1

T29

1

T30

2

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins

cp_key0_out_value

cp_key0_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

53

1

T30

1

T66

2

T70

1

auto[0]

auto[1]

38

1

T28

2

T30

1

T67

3

auto[1]

auto[0]

45

1

T28

1

T69

2

T48

1

auto[1]

auto[1]

60

1

T29

3

T30

1

T66

1

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins

cp_key1_out_value

cp_key1_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

42

1

T28

2

T29

1

T66

1

auto[0]

auto[1]

51

1

T30

2

T67

1

T68

1

auto[1]

auto[0]

51

1

T29

1

T66

1

T67

1

auto[1]

auto[1]

52

1

T28

1

T29

1

T30

1

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins

cp_key2_out_value

cp_key2_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

57

1

T28

2

T29

2

T66

1

auto[0]

auto[1]

40

1

T30

1

T66

1

T70

1

auto[1]

auto[0]

45

1

T28

1

T30

1

T66

1

auto[1]

auto[1]

54

1

T29

1

T30

1

T68

2

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8

1

T55

3

T253

1

T387

2

auto[1]

7

1

T253

2

T387

1

T318

2

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8

1

T253

3

T387

1

T318

1

auto[1]

7

1

T55

3

T387

2

T318

2

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9

1

T55

2

T253

1

T387

2

auto[1]

6

1

T55

1

T253

2

T387

1

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8

1

T55

1

T253

2

T387

2

auto[1]

7

1

T55

2

T253

1

T387

1

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9

1

T55

1

T253

2

T387

1

auto[1]

6

1

T55

2

T253

1

T387

2

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6

1

T55

1

T253

2

T387

1

auto[1]

9

1

T55

2

T253

1

T387

2

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	3	1			T253	1		T387	1		T388	1
auto[0]	auto[1]	5	1			T253	2		T318	1		T388	2
auto[1]	auto[0]	5	1			T55	3		T387	1		T318	1
auto[1]	auto[1]	2	1			T387	1		T318	1		-	-

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	6	1			T55	1		T253	1		T387	1
auto[0]	auto[1]	2	1			T253	1		T387	1		-	-
auto[1]	auto[0]	3	1			T55	1		T387	1		T388	1
auto[1]	auto[1]	4	1			T55	1		T253	1		T318	1

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	4	1			T253	1		T387	1		T318	2
auto[0]	auto[1]	2	1			T55	1		T253	1		-	-
auto[1]	auto[0]	5	1			T55	1		T253	1		T318	1
auto[1]	auto[1]	4	1			T55	1		T387	2		T388	1