Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1918

1

T35

8

T32

12

T33

3

auto[1]

651

1

T10

3

T35

10

T33

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1943

1

T10

3

T35

10

T32

9

auto[1]

626

1

T35

8

T32

3

T33

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1922

1

T10

2

T35

10

T32

12

auto[1]

647

1

T10

1

T35

8

T41

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2103

1

T35

18

T32

12

T33

3

auto[1]

466

1

T10

3

T33

1

T38

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2383

1

T10

3

T35

18

T32

9

auto[1]

186

1

T32

3

T41

1

T39

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2364

1

T10

3

T35

18

T32

12

auto[1]

205

1

T41

1

T39

9

T91

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2386

1

T10

3

T35

18

T32

9

auto[1]

183

1

T32

3

T91

3

T263

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2282

1

T10

3

T35

18

T32

12

auto[1]

287

1

T39

9

T91

1

T262

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2319

1

T10

3

T35

18

T32

12

auto[1]

250

1

T33

1

T264

14

T265

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1967

1

T10

1

T35

18

T32

12

auto[1]

602

1

T10

2

T38

1

T41

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	816	1			T10	3		T35	8		T38	26
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	63	1			T352	1		T353	2		T354	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	121	1			T33	1		T264	4		T355	9
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	20	1			T340	3		T356	5		T290	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	94	1			T262	4		T263	3		T267	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	20	1			T91	1		T339	2		T110	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	39	1			T357	3		T343	9		T358	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	10	1			T355	2		T359	1		T360	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	57	1			T91	1		T263	3		T361	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	14	1			T32	3		T344	3		T110	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	10	1			T267	1		T343	9		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	36	1			T110	2		T358	8		T351	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	7	1			T362	1		T363	5		T364	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	5	1			T265	1		T347	4		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	57	1			T264	1		T270	1		T342	5
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	24	1			T41	1		T265	4		T355	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	8	1			T365	2		T366	2		T367	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	7	1			T261	3		T368	3		T369	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	44	1			T39	7		T340	5		T370	5
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	7	1			T39	2		T356	3		T367	2
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	1	1			T267	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T368	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	25	1			T91	1		T339	12		T343	3
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T361	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T371	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	5	1			T372	1		T373	4		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

141

1

T91

1

T267

2

T126

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

129

1

T234

9

T279

11

T374

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

69

1

T263

3

T375

4

T293

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T264

2

T279

9

T374

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

50

1

T271

6

T263

3

T218

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T42

4

T234

5

T273

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T10

2

T375

2

T292

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

135

1

T271

14

T234

10

T261

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

58

1

T39

7

T117

7

T218

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

63

1

T39

2

T272

4

T265

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

64

1

T42

2

T40

3

T43

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T278

5

T346

5

T368

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T10

1

T42

1

T278

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23

1

T41

1

T119

4

T234

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

24

1

T117

4

T335

1

T274

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

160

1

T32

3

T38

20

T91

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T264

2

T376

7

T377

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

35

1

T277

4

T262

4

T120

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T273

1

T126

2

T280

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

91

1

T38

5

T293

7

T344

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T33

1

T278

3

T335

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

17

1

T40

2

T333

1

T123

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T38

1

T91

1

T124

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

81

1

T35

8

T277

8

T267

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

46

1

T109

3

T277

5

T120

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T43

10

T335

1

T378

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T379

1

T334

1

T335

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T273

2

T281

3

T282

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T380

1

T334

2

T274

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T346

1

T274

1

T378

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T277

2

T345

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded