Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

738

1

T4

9

T62

13

T83

9

auto[1]

722

1

T4

11

T62

7

T83

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

351

1

T4

4

T62

6

T83

7

from_0to1

338

1

T4

4

T62

5

T83

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

697

1

T4

8

T62

7

T83

10

auto[1]

763

1

T4

12

T62

13

T83

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

713

1

T4

7

T62

12

T83

8

auto[1]

747

1

T4

13

T62

8

T83

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

47

1

T83

1

T86

1

T93

1

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T62

1

T88

2

T325

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T62

1

T88

1

T93

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T4

2

T62

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

43

1

T62

1

T83

1

T86

1

auto[0]

from_0to1

auto[0]

auto[1]

43

1

T4

1

T62

1

T83

1

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T4

1

T62

2

T83

1

auto[0]

from_0to1

auto[1]

auto[1]

44

1

T62

1

T86

2

T88

1

auto[1]

from_1to0

auto[0]

auto[0]

44

1

T62

1

T88

1

T48

1

auto[1]

from_1to0

auto[0]

auto[1]

34

1

T86

1

T394

1

T395

1

auto[1]

from_1to0

auto[1]

auto[0]

29

1

T4

1

T62

2

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T4

1

T83

4

T86

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T83

1

T48

1

T129

4

auto[1]

from_0to1

auto[0]

auto[1]

31

1

T4

2

T83

2

T325

1

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T86

1

T88

1

T284

2

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T83

1

T88

1

T284

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

713

1

T4

10

T62

10

T83

13

auto[1]

747

1

T4

10

T62

10

T83

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

341

1

T4

5

T62

5

T83

5

from_0to1

348

1

T4

5

T62

5

T83

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

718

1

T4

10

T62

9

T83

10

auto[1]

742

1

T4

10

T62

11

T83

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721

1

T4

12

T62

9

T83

9

auto[1]

739

1

T4

8

T62

11

T83

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T83

1

T325

1

T48

1

auto[0]

from_1to0

auto[0]

auto[1]

48

1

T4

1

T62

2

T83

2

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T62

2

T86

2

T88

1

auto[0]

from_1to0

auto[1]

auto[1]

38

1

T4

1

T88

3

T93

1

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T4

1

T83

2

T86

2

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T62

1

T83

1

T394

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T62

2

T83

1

T86

1

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T83

2

T88

1

T108

2

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T4

2

T86

1

T129

1

auto[1]

from_1to0

auto[0]

auto[1]

30

1

T93

1

T284

3

T325

1

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T4

1

T62

1

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T83

1

T93

1

T325

2

auto[1]

from_0to1

auto[0]

auto[0]

37

1

T4

1

T86

2

T325

1

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T4

1

T86

1

T93

3

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T4

1

T62

1

T88

2

auto[1]

from_0to1

auto[1]

auto[1]

36

1

T4

1

T62

1

T88

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708

1

T4

8

T62

8

T83

8

auto[1]

752

1

T4

12

T62

12

T83

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

350

1

T4

3

T62

5

T83

5

from_0to1

343

1

T4

4

T62

4

T83

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721

1

T4

6

T62

9

T83

11

auto[1]

739

1

T4

14

T62

11

T83

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

731

1

T4

11

T62

10

T83

10

auto[1]

729

1

T4

9

T62

10

T83

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T4

2

T62

1

T88

2

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T83

1

T93

2

T325

1

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T83

1

T86

1

T284

1

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T62

1

T86

2

T88

1

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T86

1

T325

1

T48

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T62

1

T86

1

T93

3

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T62

2

T83

2

T93

1

auto[0]

from_0to1

auto[1]

auto[1]

47

1

T4

2

T88

2

T325

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T62

1

T93

1

T284

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T62

1

T83

2

T86

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T62

1

T83

1

T395

1

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T4

1

T88

1

T93

1

auto[1]

from_0to1

auto[0]

auto[0]

37

1

T4

1

T83

1

T88

2

auto[1]

from_0to1

auto[0]

auto[1]

32

1

T86

1

T284

1

T325

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T4

1

T83

1

T86

1

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T62

1

T83

1

T88

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

754

1

T4

12

T62

7

T83

13

auto[1]

706

1

T4

8

T62

13

T83

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

358

1

T4

5

T62

4

T83

6

from_0to1

363

1

T4

4

T62

5

T83

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

743

1

T4

9

T62

10

T83

11

auto[1]

717

1

T4

11

T62

10

T83

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

717

1

T4

11

T62

9

T83

11

auto[1]

743

1

T4

9

T62

11

T83

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T4

2

T83

1

T86

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T62

1

T83

2

T88

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T4

2

T83

1

T88

1

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T62

2

T83

1

T86

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T88

1

T93

2

T284

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T62

2

T86

1

T88

3

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T4

1

T83

2

T93

1

auto[0]

from_0to1

auto[1]

auto[1]

28

1

T4

2

T48

1

T129

1

auto[1]

from_1to0

auto[0]

auto[0]

45

1

T88

1

T93

1

T284

1

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T4

1

T83

1

T284

2

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T88

1

T93

1

T284

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T62

1

T86

3

T88

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T62

1

T83

1

T86

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T4

1

T83

2

T86

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T62

2

T86

1

T88

1

auto[1]

from_0to1

auto[1]

auto[1]

44

1

T83

1

T93

1

T48

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

724

1

T4

10

T62

11

T83

9

auto[1]

736

1

T4

10

T62

9

T83

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

345

1

T4

3

T62

5

T83

4

from_0to1

345

1

T4

4

T62

4

T83

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

718

1

T4

9

T62

12

T83

12

auto[1]

742

1

T4

11

T62

8

T83

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

694

1

T4

7

T62

14

T83

10

auto[1]

766

1

T4

13

T62

6

T83

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T62

2

T93

1

T129

1

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T4

1

T62

1

T83

2

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T4

1

T86

3

T284

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T4

1

T284

3

T325

2

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T83

1

T86

1

T284

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T88

1

T284

1

T394

1

auto[0]

from_0to1

auto[1]

auto[0]

47

1

T62

1

T83

2

T93

1

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T4

1

T86

2

T395

1

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T62

1

T88

1

T93

1

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T83

1

T86

1

T325

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T62

1

T86

1

T88

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T83

1

T93

2

T284

1

auto[1]

from_0to1

auto[0]

auto[0]

37

1

T4

1

T62

1

T83

2

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T62

1

T93

1

T284

2

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T88

1

T284

2

T325

2

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T4

2

T62

1

T86

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

725

1

T4

11

T62

10

T83

6

auto[1]

735

1

T4

9

T62

10

T83

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

336

1

T4

3

T62

4

T83

5

from_0to1

333

1

T4

3

T62

4

T83

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

706

1

T4

8

T62

11

T83

8

auto[1]

754

1

T4

12

T62

9

T83

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

745

1

T4

9

T62

12

T83

10

auto[1]

715

1

T4

11

T62

8

T83

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T86

1

T88

1

T284

1

auto[0]

from_1to0

auto[0]

auto[1]

43

1

T4

1

T62

1

T93

1

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T4

1

T86

2

T93

1

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T4

1

T62

2

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T86

1

T325

1

T48

1

auto[0]

from_0to1

auto[0]

auto[1]

33

1

T4

1

T62

1

T284

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T4

1

T62

2

T93

2

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T88

1

T93

1

T325

2

auto[1]

from_1to0

auto[0]

auto[0]

40

1

T83

1

T86

1

T129

1

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T83

2

T86

1

T88

1

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T62

1

T83

1

T88

1

auto[1]

from_1to0

auto[1]

auto[1]

41

1

T86

1

T284

2

T325

1

auto[1]

from_0to1

auto[0]

auto[0]

31

1

T62

1

T83

1

T86

2

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T4

1

T83

1

T86

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T83

3

T86

2

T394

2

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T88

3

T93

1

T284

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

701

1

T4

8

T62

9

T83

9

auto[1]

759

1

T4

12

T62

11

T83

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

353

1

T4

6

T62

6

T83

6

from_0to1

346

1

T4

6

T62

5

T83

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

733

1

T4

13

T62

8

T83

7

auto[1]

727

1

T4

7

T62

12

T83

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

737

1

T4

7

T62

10

T83

6

auto[1]

723

1

T4

13

T62

10

T83

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T86

1

T284

2

T102

4

auto[0]

from_1to0

auto[0]

auto[1]

45

1

T4

1

T62

1

T284

1

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T62

2

T83

1

T86

1

auto[0]

from_1to0

auto[1]

auto[1]

37

1

T4

2

T83

1

T88

1

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T284

1

T325

1

T394

2

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T4

2

T62

1

T83

1

auto[0]

from_0to1

auto[1]

auto[0]

40

1

T86

1

T93

2

T325

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T83

3

T86

1

T88

1

auto[1]

from_1to0

auto[0]

auto[0]

42

1

T4

1

T62

1

T83

1

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T4

2

T83

1

T325

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T62

1

T83

1

T86

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T62

1

T83

1

T86

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T4

1

T93

1

T284

1

auto[1]

from_0to1

auto[0]

auto[1]

37

1

T4

1

T62

1

T83

1

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T62

2

T93

1

T284

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T4

2

T62

1

T86

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

738

1

T4

8

T62

10

T83

12

auto[1]

722

1

T4

12

T62

10

T83

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

354

1

T4

5

T62

5

T83

4

from_0to1

352

1

T4

6

T62

5

T83

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

730

1

T4

11

T62

10

T83

13

auto[1]

730

1

T4

9

T62

10

T83

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

733

1

T4

11

T62

12

T83

5

auto[1]

727

1

T4

9

T62

8

T83

15

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

47

1

T86

3

T88

1

T93

3

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T62

1

T83

1

T93

2

auto[0]

from_1to0

auto[1]

auto[0]

36

1

T88

1

T325

2

T48

2

auto[0]

from_1to0

auto[1]

auto[1]

41

1

T4

1

T83

1

T93

1

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T4

2

T83

1

T86

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T62

1

T83

1

T88

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T88

2

T284

1

T325

1

auto[0]

from_0to1

auto[1]

auto[1]

42

1

T4

1

T62

1

T86

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T88

1

T284

1

T394

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T4

3

T83

2

T284

1

auto[1]

from_1to0

auto[1]

auto[0]

46

1

T62

3

T88

1

T284

1

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T4

1

T62

1

T86

1

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T4

1

T62

2

T325

1

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T86

1

T93

2

T284

2

auto[1]

from_0to1

auto[1]

auto[0]

45

1

T4

1

T88

2

T93

2

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T4

1

T62

1

T83

1