Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	91998	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

63337

1

T4

55

T5

7

T6

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	71804	1			T4	62		T5	3		T6	25
values[0x0]	41829	1			T4	31		T5	3		T26	35
values[0x1]	41702	1			T4	30		T5	4		T26	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	77783	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

77552

1

T4

65

T5

7

T6

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	476	1			T2	2		T10	2		T35	2
valid_sources[0x01]	420	1			T14	3		T62	1		T10	2
valid_sources[0x02]	474	1			T3	1		T8	1		T10	2
valid_sources[0x03]	1099	1			T26	1		T10	1		T61	20
valid_sources[0x04]	585	1			T15	2		T62	1		T78	1
valid_sources[0x05]	619	1			T26	1		T18	1		T10	5
valid_sources[0x06]	376	1			T62	1		T28	1		T10	1
valid_sources[0x07]	457	1			T25	1		T9	1		T10	2
valid_sources[0x08]	447	1			T15	2		T25	1		T83	1
valid_sources[0x09]	439	1			T83	1		T10	1		T35	3
valid_sources[0x0a]	411	1			T15	2		T18	2		T25	2
valid_sources[0x0b]	524	1			T26	1		T83	1		T10	3
valid_sources[0x0c]	484	1			T15	1		T25	1		T83	1
valid_sources[0x0d]	451	1			T25	1		T9	1		T83	1
valid_sources[0x0e]	1606	1			T15	1		T18	1		T27	1
valid_sources[0x0f]	505	1			T26	1		T3	1		T23	2
valid_sources[0x10]	451	1			T62	2		T28	1		T10	3
valid_sources[0x11]	537	1			T15	1		T10	3		T86	1
valid_sources[0x12]	558	1			T17	1		T60	17		T10	3
valid_sources[0x13]	528	1			T83	1		T10	1		T86	1
valid_sources[0x14]	550	1			T20	12		T83	1		T35	3
valid_sources[0x15]	494	1			T83	1		T86	1		T32	5
valid_sources[0x16]	403	1			T8	1		T10	1		T78	1
valid_sources[0x17]	460	1			T25	1		T9	1		T83	1
valid_sources[0x18]	440	1			T18	1		T10	1		T86	1
valid_sources[0x19]	515	1			T60	9		T10	3		T85	1
valid_sources[0x1a]	564	1			T26	1		T18	1		T62	2
valid_sources[0x1b]	422	1			T31	2		T10	2		T35	2
valid_sources[0x1c]	630	1			T3	1		T25	1		T60	100
valid_sources[0x1d]	503	1			T17	1		T10	1		T85	2
valid_sources[0x1e]	444	1			T17	1		T62	1		T83	1
valid_sources[0x1f]	475	1			T2	7		T62	2		T10	3
valid_sources[0x20]	1204	1			T26	1		T9	1		T83	3
valid_sources[0x21]	548	1			T18	3		T3	1		T10	1
valid_sources[0x22]	396	1			T15	1		T27	1		T3	1
valid_sources[0x23]	1325	1			T15	1		T17	1		T18	1
valid_sources[0x24]	956	1			T17	1		T25	1		T60	3
valid_sources[0x25]	485	1			T63	1		T3	2		T83	1
valid_sources[0x26]	525	1			T15	1		T62	1		T8	1
valid_sources[0x27]	510	1			T8	1		T10	1		T35	1
valid_sources[0x28]	444	1			T83	2		T10	1		T35	1
valid_sources[0x29]	535	1			T26	1		T25	1		T60	20
valid_sources[0x2a]	445	1			T35	1		T32	1		T94	9
valid_sources[0x2b]	506	1			T15	1		T31	1		T83	1
valid_sources[0x2c]	459	1			T10	3		T35	2		T32	4
valid_sources[0x2d]	445	1			T26	1		T18	1		T83	1
valid_sources[0x2e]	1382	1			T60	20		T10	2		T84	1
valid_sources[0x2f]	464	1			T3	1		T8	1		T10	1
valid_sources[0x30]	487	1			T17	2		T27	2		T62	1
valid_sources[0x31]	589	1			T2	7		T27	1		T10	3
valid_sources[0x32]	2064	1			T26	2		T27	1		T29	11
valid_sources[0x33]	439	1			T62	1		T10	2		T86	1
valid_sources[0x34]	538	1			T26	1		T83	1		T243	1
valid_sources[0x35]	523	1			T27	1		T62	2		T25	1
valid_sources[0x36]	380	1			T15	1		T27	1		T83	1
valid_sources[0x37]	503	1			T27	3		T62	3		T245	1
valid_sources[0x38]	486	1			T26	1		T63	1		T3	1
valid_sources[0x39]	520	1			T83	1		T86	2		T35	3
valid_sources[0x3a]	431	1			T62	1		T10	3		T32	2
valid_sources[0x3b]	474	1			T62	1		T25	1		T7	19
valid_sources[0x3c]	495	1			T27	2		T3	1		T60	22
valid_sources[0x3d]	518	1			T26	1		T83	1		T10	3
valid_sources[0x3e]	478	1			T26	1		T62	1		T31	1
valid_sources[0x3f]	394	1			T26	1		T62	1		T60	1
valid_sources[0x40]	459	1			T26	1		T10	3		T84	2
valid_sources[0x41]	413	1			T62	1		T8	1		T72	4
valid_sources[0x42]	1323	1			T31	2		T29	12		T83	1
valid_sources[0x43]	502	1			T26	1		T18	1		T83	1
valid_sources[0x44]	490	1			T26	1		T15	1		T18	1
valid_sources[0x45]	435	1			T25	1		T83	2		T10	2
valid_sources[0x46]	534	1			T26	1		T27	1		T62	2
valid_sources[0x47]	535	1			T26	1		T60	7		T10	3
valid_sources[0x48]	419	1			T10	4		T61	2		T78	2
valid_sources[0x49]	490	1			T26	1		T10	1		T84	1
valid_sources[0x4a]	492	1			T26	1		T27	2		T9	2
valid_sources[0x4b]	487	1			T62	3		T83	1		T10	2
valid_sources[0x4c]	510	1			T8	1		T10	3		T35	5
valid_sources[0x4d]	620	1			T62	2		T3	1		T65	2
valid_sources[0x4e]	455	1			T62	1		T25	1		T10	1
valid_sources[0x4f]	637	1			T4	123		T26	1		T22	5
valid_sources[0x50]	388	1			T3	1		T84	1		T35	2
valid_sources[0x51]	517	1			T15	1		T62	1		T10	1
valid_sources[0x52]	491	1			T62	1		T10	3		T78	1
valid_sources[0x53]	482	1			T15	1		T29	11		T60	3
valid_sources[0x54]	407	1			T3	1		T10	2		T97	1
valid_sources[0x55]	405	1			T10	3		T98	1		T86	2
valid_sources[0x56]	456	1			T15	1		T25	1		T29	7
valid_sources[0x57]	506	1			T18	2		T27	1		T62	1
valid_sources[0x58]	580	1			T27	1		T71	2		T84	1
valid_sources[0x59]	451	1			T15	1		T18	3		T86	1
valid_sources[0x5a]	528	1			T26	1		T17	2		T27	3
valid_sources[0x5b]	610	1			T62	2		T3	1		T10	1
valid_sources[0x5c]	512	1			T28	1		T29	1		T8	1
valid_sources[0x5d]	372	1			T26	1		T62	1		T10	3
valid_sources[0x5e]	915	1			T27	1		T62	1		T10	2
valid_sources[0x5f]	460	1			T62	1		T10	3		T85	1
valid_sources[0x60]	556	1			T15	2		T60	2		T10	1
valid_sources[0x61]	505	1			T9	1		T35	2		T32	3
valid_sources[0x62]	544	1			T2	7		T10	2		T35	2
valid_sources[0x63]	524	1			T62	2		T83	1		T10	4
valid_sources[0x64]	437	1			T56	1		T25	1		T65	1
valid_sources[0x65]	481	1			T6	2		T17	1		T18	2
valid_sources[0x66]	1773	1			T27	2		T3	1		T83	1
valid_sources[0x67]	686	1			T18	4		T83	1		T10	3
valid_sources[0x68]	450	1			T26	1		T62	1		T28	1
valid_sources[0x69]	494	1			T10	2		T32	4		T87	2
valid_sources[0x6a]	731	1			T15	2		T21	1		T10	2
valid_sources[0x6b]	447	1			T60	4		T9	1		T10	4
valid_sources[0x6c]	545	1			T3	1		T10	5		T78	1
valid_sources[0x6d]	522	1			T27	1		T62	3		T83	1
valid_sources[0x6e]	413	1			T17	2		T27	1		T29	2
valid_sources[0x6f]	489	1			T63	1		T62	1		T10	1
valid_sources[0x70]	502	1			T18	1		T27	1		T62	1
valid_sources[0x71]	400	1			T26	1		T27	2		T62	1
valid_sources[0x72]	462	1			T26	1		T15	1		T28	1
valid_sources[0x73]	455	1			T60	20		T10	1		T35	2
valid_sources[0x74]	459	1			T25	1		T8	1		T139	6
valid_sources[0x75]	526	1			T26	1		T2	6		T25	1
valid_sources[0x76]	448	1			T27	1		T3	2		T28	1
valid_sources[0x77]	627	1			T83	3		T10	2		T61	20
valid_sources[0x78]	518	1			T5	1		T25	1		T83	1
valid_sources[0x79]	558	1			T83	1		T10	2		T84	1
valid_sources[0x7a]	517	1			T18	2		T62	1		T31	2
valid_sources[0x7b]	481	1			T8	1		T10	3		T35	1
valid_sources[0x7c]	1023	1			T17	1		T62	3		T10	2
valid_sources[0x7d]	499	1			T10	4		T35	1		T32	6
valid_sources[0x7e]	362	1			T65	2		T10	2		T75	3
valid_sources[0x7f]	478	1			T26	1		T62	1		T83	1
valid_sources[0x80]	481	1			T26	2		T62	2		T25	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35981

1

T4

35

T5

3

T6

12

values[0x0]

all_enables

biggest_size

16852

1

T4

15

T5

3

T26

12

values[0x1]

all_enables

biggest_size

10504

1

T4

5

T5

1

T26

5