Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	908178958	473	0	0
auto_block_debounce_ctl_rd_A	908178958	491	0	0
auto_block_out_ctl_rd_A	908178958	432	0	0
com_det_ctl_0_rd_A	908178958	2487	0	0
com_det_ctl_1_rd_A	908178958	2330	0	0
com_det_ctl_2_rd_A	908178958	2389	0	0
com_det_ctl_3_rd_A	908178958	2328	0	0
com_out_ctl_0_rd_A	908178958	2330	0	0
com_out_ctl_1_rd_A	908178958	2432	0	0
com_out_ctl_2_rd_A	908178958	2419	0	0
com_out_ctl_3_rd_A	908178958	2256	0	0
com_pre_det_ctl_0_rd_A	908178958	255	0	0
com_pre_det_ctl_1_rd_A	908178958	278	0	0
com_pre_det_ctl_2_rd_A	908178958	264	0	0
com_pre_det_ctl_3_rd_A	908178958	240	0	0
com_pre_sel_ctl_0_rd_A	908178958	2246	0	0
com_pre_sel_ctl_1_rd_A	908178958	2176	0	0
com_pre_sel_ctl_2_rd_A	908178958	2518	0	0
com_pre_sel_ctl_3_rd_A	908178958	2354	0	0
com_sel_ctl_0_rd_A	908178958	2418	0	0
com_sel_ctl_1_rd_A	908178958	2396	0	0
com_sel_ctl_2_rd_A	908178958	2326	0	0
com_sel_ctl_3_rd_A	908178958	2493	0	0
ec_rst_ctl_rd_A	908178958	1019	0	0
intr_enable_rd_A	908178958	438	0	0
key_intr_ctl_rd_A	908178958	418	0	0
key_intr_debounce_ctl_rd_A	908178958	259	0	0
key_invert_ctl_rd_A	908178958	1543	0	0
pin_allowed_ctl_rd_A	908178958	1641	0	0
pin_out_ctl_rd_A	908178958	1590	0	0
pin_out_value_rd_A	908178958	1541	0	0
regwen_rd_A	908178958	288	0	0
ulp_ac_debounce_ctl_rd_A	908178958	425	0	0
ulp_ctl_rd_A	908178958	360	0	0
ulp_lid_debounce_ctl_rd_A	908178958	393	0	0
ulp_pwrb_debounce_ctl_rd_A	908178958	416	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	473	0	0
T9	50526	0	0	0
T10	126105	0	0	0
T23	48336	0	0	0
T48	0	12	0	0
T57	44904	0	0	0
T58	0	8	0	0
T59	0	8	0	0
T60	567438	18	0	0
T61	92943	3	0	0
T78	57014	0	0	0
T83	206404	0	0	0
T84	248099	0	0	0
T94	0	23	0	0
T102	0	16	0	0
T139	89162	0	0	0
T287	0	9	0	0
T310	0	5	0	0
T311	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	491	0	0
T12	97229	0	0	0
T13	239969	0	0	0
T30	347669	12	0	0
T35	209136	0	0	0
T52	226890	0	0	0
T68	0	2	0	0
T69	0	12	0	0
T70	0	13	0	0
T75	196676	0	0	0
T85	131023	0	0	0
T86	125703	0	0	0
T98	46341	0	0	0
T102	0	40	0	0
T105	0	15	0	0
T141	0	11	0	0
T242	49037	0	0	0
T312	0	4	0	0
T313	0	57	0	0
T314	0	15	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	432	0	0
T12	97229	0	0	0
T13	239969	0	0	0
T30	347669	15	0	0
T35	209136	0	0	0
T52	226890	0	0	0
T68	0	7	0	0
T69	0	13	0	0
T75	196676	0	0	0
T85	131023	0	0	0
T86	125703	0	0	0
T98	46341	0	0	0
T102	0	46	0	0
T105	0	11	0	0
T141	0	14	0	0
T242	49037	0	0	0
T312	0	12	0	0
T313	0	33	0	0
T314	0	9	0	0
T315	0	3	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2487	0	0
T10	126105	46	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	36	0	0
T35	0	50	0	0
T40	0	62	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	43	0	0
T262	0	34	0	0
T263	0	46	0	0
T272	0	76	0	0
T278	0	64	0	0
T313	0	38	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2330	0	0
T10	126105	63	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	38	0	0
T35	0	66	0	0
T40	0	95	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	42	0	0
T262	0	20	0	0
T263	0	44	0	0
T272	0	55	0	0
T278	0	16	0	0
T313	0	33	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2389	0	0
T10	126105	50	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	36	0	0
T35	0	77	0	0
T40	0	64	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	57	0	0
T262	0	28	0	0
T263	0	59	0	0
T272	0	79	0	0
T278	0	42	0	0
T313	0	33	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2328	0	0
T10	126105	54	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	46	0	0
T35	0	73	0	0
T40	0	55	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	37	0	0
T262	0	35	0	0
T263	0	38	0	0
T272	0	61	0	0
T278	0	64	0	0
T313	0	31	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2330	0	0
T10	126105	55	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	34	0	0
T35	0	51	0	0
T40	0	90	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	60	0	0
T262	0	25	0	0
T263	0	50	0	0
T272	0	93	0	0
T278	0	35	0	0
T313	0	34	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2432	0	0
T10	126105	32	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	55	0	0
T35	0	88	0	0
T40	0	59	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	43	0	0
T262	0	36	0	0
T263	0	44	0	0
T272	0	65	0	0
T278	0	69	0	0
T313	0	35	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2419	0	0
T10	126105	50	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	41	0	0
T35	0	78	0	0
T40	0	64	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	48	0	0
T262	0	29	0	0
T263	0	50	0	0
T272	0	72	0	0
T278	0	48	0	0
T313	0	27	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2256	0	0
T10	126105	52	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	49	0	0
T35	0	68	0	0
T40	0	70	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	45	0	0
T262	0	45	0	0
T263	0	43	0	0
T272	0	57	0	0
T278	0	19	0	0
T313	0	31	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	255	0	0
T40	344201	0	0	0
T59	468381	0	0	0
T102	436333	39	0	0
T105	0	16	0	0
T109	171100	0	0	0
T178	0	16	0	0
T201	60605	0	0	0
T202	85703	0	0	0
T203	31660	0	0	0
T204	58719	0	0	0
T205	51346	0	0	0
T206	22780	0	0	0
T305	0	1	0	0
T313	0	36	0	0
T316	0	12	0	0
T317	0	23	0	0
T318	0	31	0	0
T319	0	19	0	0
T320	0	22	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	278	0	0
T40	344201	0	0	0
T59	468381	0	0	0
T102	436333	39	0	0
T105	0	14	0	0
T109	171100	0	0	0
T178	0	28	0	0
T201	60605	0	0	0
T202	85703	0	0	0
T203	31660	0	0	0
T204	58719	0	0	0
T205	51346	0	0	0
T206	22780	0	0	0
T305	0	18	0	0
T313	0	42	0	0
T316	0	12	0	0
T317	0	15	0	0
T318	0	37	0	0
T319	0	23	0	0
T320	0	26	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	264	0	0
T40	344201	0	0	0
T59	468381	0	0	0
T102	436333	35	0	0
T105	0	12	0	0
T109	171100	0	0	0
T178	0	24	0	0
T201	60605	0	0	0
T202	85703	0	0	0
T203	31660	0	0	0
T204	58719	0	0	0
T205	51346	0	0	0
T206	22780	0	0	0
T305	0	6	0	0
T313	0	32	0	0
T316	0	10	0	0
T317	0	30	0	0
T318	0	38	0	0
T319	0	24	0	0
T320	0	14	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	240	0	0
T40	344201	0	0	0
T59	468381	0	0	0
T102	436333	37	0	0
T105	0	33	0	0
T109	171100	0	0	0
T178	0	20	0	0
T201	60605	0	0	0
T202	85703	0	0	0
T203	31660	0	0	0
T204	58719	0	0	0
T205	51346	0	0	0
T206	22780	0	0	0
T305	0	17	0	0
T313	0	38	0	0
T316	0	5	0	0
T317	0	19	0	0
T318	0	12	0	0
T319	0	21	0	0
T320	0	17	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2246	0	0
T10	126105	34	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	42	0	0
T35	0	80	0	0
T40	0	46	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	38	0	0
T262	0	33	0	0
T263	0	51	0	0
T272	0	75	0	0
T278	0	38	0	0
T313	0	37	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2176	0	0
T10	126105	32	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	51	0	0
T35	0	78	0	0
T40	0	74	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	37	0	0
T262	0	23	0	0
T263	0	39	0	0
T272	0	56	0	0
T278	0	32	0	0
T313	0	39	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2518	0	0
T10	126105	76	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	44	0	0
T35	0	81	0	0
T40	0	74	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	39	0	0
T262	0	23	0	0
T263	0	57	0	0
T272	0	71	0	0
T278	0	53	0	0
T313	0	56	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2354	0	0
T10	126105	51	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	50	0	0
T35	0	81	0	0
T40	0	86	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	42	0	0
T262	0	23	0	0
T263	0	39	0	0
T272	0	75	0	0
T278	0	53	0	0
T313	0	29	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2418	0	0
T10	126105	65	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	37	0	0
T35	0	81	0	0
T40	0	61	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	33	0	0
T262	0	27	0	0
T263	0	44	0	0
T272	0	48	0	0
T278	0	47	0	0
T313	0	40	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2396	0	0
T10	126105	36	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	34	0	0
T35	0	69	0	0
T40	0	64	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	29	0	0
T262	0	32	0	0
T263	0	36	0	0
T272	0	55	0	0
T278	0	38	0	0
T313	0	46	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2326	0	0
T10	126105	50	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	50	0	0
T35	0	62	0	0
T40	0	56	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	48	0	0
T262	0	38	0	0
T263	0	29	0	0
T272	0	52	0	0
T278	0	32	0	0
T313	0	51	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	2493	0	0
T10	126105	34	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T33	0	60	0	0
T35	0	81	0	0
T40	0	84	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T84	248099	0	0	0
T85	131023	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T98	46341	0	0	0
T102	0	46	0	0
T262	0	31	0	0
T263	0	54	0	0
T272	0	61	0	0
T278	0	27	0	0
T313	0	33	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	1019	0	0
T9	50526	0	0	0
T10	126105	10	0	0
T23	48336	0	0	0
T33	0	10	0	0
T35	0	4	0	0
T40	0	16	0	0
T57	44904	0	0	0
T61	92943	0	0	0
T64	0	1	0	0
T78	57014	0	0	0
T83	206404	0	0	0
T84	248099	0	0	0
T96	202300	0	0	0
T102	0	28	0	0
T128	0	4	0	0
T139	89162	2	0	0
T202	0	1	0	0
T321	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	438	0	0
T40	344201	0	0	0
T59	468381	0	0	0
T102	436333	38	0	0
T105	0	40	0	0
T109	171100	0	0	0
T113	0	55	0	0
T178	0	35	0	0
T201	60605	0	0	0
T202	85703	0	0	0
T203	31660	0	0	0
T204	58719	0	0	0
T205	51346	0	0	0
T206	22780	0	0	0
T209	0	9	0	0
T313	0	46	0	0
T316	0	14	0	0
T317	0	23	0	0
T318	0	30	0	0
T322	0	33	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	418	0	0
T1	102873	4	0	0
T2	220239	0	0	0
T14	133686	0	0	0
T15	237481	0	0	0
T16	12196	0	0	0
T17	72192	0	0	0
T18	52945	0	0	0
T19	107297	0	0	0
T20	193146	0	0	0
T21	211167	0	0	0
T49	0	6	0	0
T51	0	4	0	0
T64	0	113	0	0
T102	0	36	0	0
T105	0	18	0	0
T159	0	4	0	0
T216	0	4	0	0
T313	0	28	0	0
T316	0	12	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	259	0	0
T40	344201	0	0	0
T59	468381	0	0	0
T102	436333	44	0	0
T105	0	13	0	0
T109	171100	0	0	0
T178	0	11	0	0
T201	60605	0	0	0
T202	85703	0	0	0
T203	31660	0	0	0
T204	58719	0	0	0
T205	51346	0	0	0
T206	22780	0	0	0
T298	0	46	0	0
T305	0	19	0	0
T313	0	31	0	0
T317	0	26	0	0
T318	0	26	0	0
T319	0	13	0	0
T320	0	30	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	1543	0	0
T7	369263	0	0	0
T8	464574	0	0	0
T23	48336	0	0	0
T25	115303	65	0	0
T29	114833	0	0	0
T31	51848	0	0	0
T60	567438	0	0	0
T65	55657	0	0	0
T72	53540	0	0	0
T80	0	53	0	0
T82	0	74	0	0
T102	0	89	0	0
T105	0	147	0	0
T139	89162	0	0	0
T235	0	72	0	0
T313	0	22	0	0
T322	0	58	0	0
T323	0	80	0	0
T324	0	72	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	1641	0	0
T10	126105	0	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T57	44904	0	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T83	206404	60	0	0
T84	248099	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T102	0	237	0	0
T105	0	20	0	0
T239	0	79	0	0
T313	0	42	0	0
T316	0	19	0	0
T325	0	52	0	0
T326	0	61	0	0
T327	0	68	0	0
T328	0	83	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	1590	0	0
T10	126105	0	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T57	44904	0	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T83	206404	59	0	0
T84	248099	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T102	0	264	0	0
T105	0	13	0	0
T239	0	88	0	0
T313	0	31	0	0
T316	0	36	0	0
T325	0	38	0	0
T326	0	52	0	0
T327	0	61	0	0
T328	0	57	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	1541	0	0
T10	126105	0	0	0
T11	56113	0	0	0
T30	347669	0	0	0
T57	44904	0	0	0
T61	92943	0	0	0
T78	57014	0	0	0
T83	206404	50	0	0
T84	248099	0	0	0
T96	202300	0	0	0
T97	23677	0	0	0
T102	0	236	0	0
T105	0	28	0	0
T239	0	68	0	0
T313	0	31	0	0
T316	0	60	0	0
T325	0	33	0	0
T326	0	61	0	0
T327	0	58	0	0
T328	0	64	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	288	0	0
T40	344201	0	0	0
T59	468381	0	0	0
T102	436333	40	0	0
T105	0	34	0	0
T109	171100	0	0	0
T178	0	7	0	0
T201	60605	0	0	0
T202	85703	0	0	0
T203	31660	0	0	0
T204	58719	0	0	0
T205	51346	0	0	0
T206	22780	0	0	0
T305	0	26	0	0
T313	0	33	0	0
T316	0	12	0	0
T317	0	23	0	0
T318	0	23	0	0
T319	0	29	0	0
T320	0	22	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	425	0	0
T2	220239	9	0	0
T3	238349	0	0	0
T19	107297	0	0	0
T20	193146	0	0	0
T21	211167	0	0	0
T23	0	5	0	0
T27	125546	0	0	0
T28	404128	0	0	0
T56	50643	0	0	0
T62	241272	0	0	0
T63	114098	0	0	0
T75	0	7	0	0
T102	0	47	0	0
T105	0	47	0	0
T113	0	4	0	0
T313	0	40	0	0
T316	0	19	0	0
T329	0	7	0	0
T330	0	9	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	360	0	0
T2	220239	27	0	0
T3	238349	0	0	0
T19	107297	0	0	0
T20	193146	0	0	0
T21	211167	0	0	0
T23	0	8	0	0
T27	125546	0	0	0
T28	404128	0	0	0
T56	50643	0	0	0
T62	241272	0	0	0
T63	114098	0	0	0
T102	0	31	0	0
T105	0	3	0	0
T113	0	2	0	0
T142	0	7	0	0
T313	0	29	0	0
T316	0	12	0	0
T330	0	1	0	0
T331	0	7	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	393	0	0
T2	220239	15	0	0
T3	238349	0	0	0
T19	107297	0	0	0
T20	193146	0	0	0
T21	211167	0	0	0
T23	0	2	0	0
T27	125546	0	0	0
T28	404128	0	0	0
T56	50643	0	0	0
T62	241272	0	0	0
T63	114098	0	0	0
T102	0	38	0	0
T105	0	7	0	0
T113	0	2	0	0
T142	0	11	0	0
T194	0	4	0	0
T313	0	42	0	0
T316	0	19	0	0
T330	0	10	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	908178958	416	0	0
T2	220239	24	0	0
T3	238349	0	0	0
T19	107297	0	0	0
T20	193146	0	0	0
T21	211167	0	0	0
T23	0	9	0	0
T27	125546	0	0	0
T28	404128	0	0	0
T56	50643	0	0	0
T62	241272	0	0	0
T63	114098	0	0	0
T102	0	32	0	0
T105	0	16	0	0
T113	0	6	0	0
T142	0	10	0	0
T313	0	49	0	0
T316	0	25	0	0
T329	0	4	0	0
T330	0	8	0	0