Unified Coverage Report :: Module

Line Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_prim_flop_2sync_input.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_prim_flop_2sync_input.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_prim_flop_2sync_input.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_prim_flop_2sync_input.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00



17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
19         1/1                q_o <= ResetValue;
           Tests:       T4 T5 T6 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T4 T5 T6

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_intr.u_match_sync.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00



18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children