4674f625b3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 12.200s | 2.112ms | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 14.800s | 2.456ms | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 14.370s | 2.424ms | 5 | 5 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 8.050s | 2.266ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 110 | 165 | 66.67 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 12.425m | 219.382ms | 50 | 50 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 9.571m | 221.062ms | 96 | 100 | 96.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 6.272m | 231.829ms | 49 | 50 | 98.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 10.064m | 370.492ms | 50 | 50 | 100.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 14.580s | 2.511ms | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 13.020s | 2.173ms | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 13.113m | 948.239ms | 49 | 50 | 98.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 15.240s | 2.613ms | 50 | 50 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 6.885m | 4.121s | 48 | 50 | 96.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 2.648m | 42.591ms | 2 | 2 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 7.852m | 157.164ms | 49 | 50 | 98.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 12.560s | 2.012ms | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| sysrst_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| sysrst_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 593 | 692 | 85.69 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 1.818m | 42.015ms | 5 | 5 | 100.00 |
| sysrst_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 5 | 25 | 20.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 1.848m | 1.753s | 45 | 50 | 90.00 |
| V3 | TOTAL | 45 | 50 | 90.00 | |||
| TOTAL | 753 | 932 | 80.79 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 4 | 44.44 |
| V2 | 15 | 15 | 7 | 46.67 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.39 | 98.86 | 94.55 | 100.00 | 98.08 | 98.26 | 98.94 | 86.07 |
Job killed most likely because its dependent job failed. has 165 failures:
0.sysrst_ctrl_tl_errors.101522121345871234705123540844496103995275150114925752975535733322122943334477
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest/run.log
1.sysrst_ctrl_tl_errors.55220934484055781009923048840720060736218021079756183746474945414551115489970
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest/run.log
... and 18 more failures.
0.sysrst_ctrl_tl_intg_err.21309111893879301752570210677815562527757677063601377990541011041046098918772
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest/run.log
1.sysrst_ctrl_tl_intg_err.44203350805386668175359674757085074897135433958342437147785361598525175575964
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest/run.log
... and 18 more failures.
0.sysrst_ctrl_intr_test.106009040550379172314955663785913178698721918263541615939373781424451898592861
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest/run.log
1.sysrst_ctrl_intr_test.38613461966969571316248577563270367301009769420523645573199186650534218590230
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest/run.log
... and 48 more failures.
0.sysrst_ctrl_csr_hw_reset.51244185138245323930183936016330781707628236754692717916651646768683474894791
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest/run.log
1.sysrst_ctrl_csr_hw_reset.19673952623237220320509758494011759135088717599857814554448709589228281370599
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest/run.log
... and 3 more failures.
0.sysrst_ctrl_csr_rw.5553431377005303828330869110044176217188073601846287035929764239294029542616
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest/run.log
1.sysrst_ctrl_csr_rw.33881063182948096992935988550363537890135263340604617357405437752879492345125
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest/run.log
... and 18 more failures.
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 3 failures:
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
0.sysrst_ctrl_stress_all_with_rand_reset.45545759926216223487399740888836769209832279152619709735153650380805442883562
Line 408, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 195846688446 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 705824188446 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 705824188446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_ultra_low_pwr has 2 failures.
24.sysrst_ctrl_ultra_low_pwr.100922841146200900339565867371127211261955552616312392969759603090884110820187
Line 372, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 7696082545 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 8023582545 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_INFO @ 9253582545 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 9270293974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.sysrst_ctrl_ultra_low_pwr.47311900774652856755364962412162779548975496592451995439997793811591457078128
Line 371, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2428089184 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 3875589184 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3875589184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:35) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (* [*] vs * [*]) has 2 failures:
19.sysrst_ctrl_stress_all_with_rand_reset.70221363296883520698187568308263025874065017434870510399273657222977399559180
Line 384, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4071653922 ps: (sysrst_ctrl_pin_access_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 4071653922 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4071653922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.sysrst_ctrl_stress_all_with_rand_reset.1364848481069660350583130141327636887142083889047086523206749892936971260648
Line 456, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1753404816379 ps: (sysrst_ctrl_pin_access_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 1753404816379 ps: (sysrst_ctrl_pin_access_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key1_in == rdata_key1_in (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1753404816379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[SV-LCM-PND] Package not defined has 1 failures:
cover_reg_top
Line 907, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/cover_reg_top/build.log
Error-[SV-LCM-PND] Package not defined
../src/lowrisc_ip_lc_ctrl_pkg_0.1/rtl/lc_ctrl_pkg.sv, 11
lc_ctrl_pkg, "lc_ctrl_state_pkg::"
Package scope resolution failed. Token 'lc_ctrl_state_pkg' is not a package.
Originating module 'lc_ctrl_pkg'.
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-* has 1 failures:
3.sysrst_ctrl_combo_detect_with_pre_cond.113406747924825023656739864035316277420662411558248328092058152429794380452323
Line 381, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 13818202370 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
UVM_INFO @ 13828202370 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
UVM_INFO @ 13968202370 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 13988202370 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 24030691542 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x20
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 1 failures:
6.sysrst_ctrl_stress_all_with_rand_reset.84195224547535253405753804104912228550083670956334066557128545002511438167997
Line 409, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9239597671 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 9239597671 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 9239597671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (* [*] vs * [*]) has 1 failures:
6.sysrst_ctrl_stress_all.97302705689748521078620262799625106242047150984209474223700956237797603052799
Line 374, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 4187391864 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4307625306 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 20
UVM_INFO @ 4562391864 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:40
UVM_INFO @ 4662503145 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 62
UVM_INFO @ 5237391864 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:102
Job timed out after * minutes has 1 failures:
10.sysrst_ctrl_ec_pwr_on_rst.22302185047176183578629739753026824650333722770703510734826847876971783725602
Log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:115) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (* [*] vs * [*]) has 1 failures:
41.sysrst_ctrl_stress_all_with_rand_reset.85666868266179022146193192072488758881744608386670183733487141784352119550119
Line 408, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6153610038 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 6153610038 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:121) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_pwrb_in == inv_pwrb_out (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6153610038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (* [*] vs * [*]) has 1 failures:
44.sysrst_ctrl_auto_blk_key_output.33432972961626977192095593186175558408792314185768186978754217301182935176429
Line 373, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest/run.log
UVM_ERROR @ 2571120478 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 2571120478 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2571120478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-* has 1 failures:
85.sysrst_ctrl_combo_detect_with_pre_cond.40859093367550636476867295327849148915034109707452631274553881205410737927636
Line 394, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 15432923056 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-4
UVM_INFO @ 15627923056 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 15647923056 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 25675288168 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x29
UVM_INFO @ 25675510390 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x23
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:
87.sysrst_ctrl_combo_detect_with_pre_cond.82113075570195459633694515417639439530350858313378616587230560491162803768539
Line 390, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 23954195983 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 23954195983 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 23954195983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o has 1 failures:
98.sysrst_ctrl_combo_detect_with_pre_cond.111138288429036737534536293543483044167380100151794913126838026021510619601789
Line 411, in log /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 29567065108 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == 1) Unexpected L2H transition of ec_rst_l_o
UVM_INFO @ 29567065108 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 29587065108 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 39652953519 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x23
UVM_INFO @ 39652995185 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xd