Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1028010
Category 01028010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1028010
Severity 01028010

Summary for Assertions
NUMBERPERCENT
Total Number1028100.00
Uncovered60.58
Success102299.42
Failure00.00
Incomplete10.10
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001291986092254503400
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 001291985542571900
tb.dut.tlul_assert_device.gen_device.contigMask_M 0012919860921864883100
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00129198609218439400
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 001291985542622400
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0012919860922024353100
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00129198609252105600
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0012919860922024353100
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00129198609252105600
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00129198609252105600
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00129198609252105600
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 001291985542347900
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 001291985542310100
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0091291200
tb.dut.u_reg.en2addrHit 00129198554225781600
tb.dut.u_reg.reAfterRv 00129198554225781600
tb.dut.u_reg.rePulse 00129198554213971500
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A 001291985542142083100
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A 001291985542135300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542135300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930135300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930127700
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542136300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A 001291985542126232300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A 001291985542122400
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542122400
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930122400
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930114400
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542123400
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0091291200
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A 001291985542194206400
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A 001291985542190800
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542190800
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930190800
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930183100
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542191800
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A 001291985542191108400
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A 001291985542188700
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542188700
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930188700
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930180500
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542189600
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A 001291985542185503700
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A 001291985542184100
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542184100
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930184100
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930176400
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542184900
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A 001291985542189194100
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A 001291985542188100
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542188100
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930188100
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930179900
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542189100
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A 001291985542192001800
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A 001291985542192500
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542192500
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930192500
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930184800
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542193300
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A 001291985542185702600
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A 001291985542184300
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542184300
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930184300
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930176500
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542185100
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A 001291985542185761500
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A 001291985542185100
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542185100
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930185100
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930177000
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542186000
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A 001291985542189068500
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A 001291985542188500
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542188500
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930188500
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930180600
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542189500
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A 001291985542146608500
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A 001291985542141900
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542141900
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930141900
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930133800
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542142700
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A 001291985542143407000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A 001291985542139900
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542139900
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930139900
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930132000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542140900
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A 001291985542143575100
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A 001291985542140800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542140800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930140800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930133100
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542141900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A 001291985542139170300
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A 001291985542136700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542136700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930136700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930128500
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542137500
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A 001291985542684374100
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A 001291985542701000
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542701000
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930701000
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930692800
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542702000
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A 001291985542695133000
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A 001291985542716300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542716300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930716300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930708000
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542717200
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A 001291985542673915200
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A 001291985542699600
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542699600
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930699600
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930691000
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542700500
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A 001291985542681410700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A 001291985542707200
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542707200
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930707200
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930698700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542708200
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A 001291985542739955400
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A 001291985542754400
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542754400
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930754400
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930746100
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542755400
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A 001291985542746883400
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A 001291985542763800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542763800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930763800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930755300
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542764900
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A 001291985542723401800
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A 001291985542746100
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542746100
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930746100
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930737200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542746900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A 001291985542739482700
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A 001291985542758900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542758900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930758900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930750300
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542759700
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A 001291985542195107400
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A 001291985542196300
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A 001291985542129154311200
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001291985542196300
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007724930196300
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 007724930188400
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001291985542197400
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A 001291985542115738300
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A 007724930706809300
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A 001291985542114000
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A 001291985542129154311200
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