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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	912	912	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	1291986092	2545034	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	1291985542	5719	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	1291986092	18648831	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	1291986092	184394	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	1291985542	6224	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	1291986092	20243531	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	1291986092	521056	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	1291986092	20243531	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	1291986092	521056	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	1291986092	521056	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	1291986092	521056	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	1291985542	3479	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	1291985542	3101	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	912	912	0	0
tb.dut.u_reg.en2addrHit	0	0	1291985542	257816	0	0
tb.dut.u_reg.reAfterRv	0	0	1291985542	257816	0	0
tb.dut.u_reg.rePulse	0	0	1291985542	139715	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A	0	0	1291985542	1420831	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A	0	0	1291985542	1353	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1353	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1353	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1277	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1363	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A	0	0	1291985542	1262323	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A	0	0	1291985542	1224	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1224	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1224	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1144	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1234	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	912	912	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A	0	0	1291985542	1942064	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A	0	0	1291985542	1908	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1908	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1908	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1831	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1918	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A	0	0	1291985542	1911084	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A	0	0	1291985542	1887	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1887	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1887	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1805	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1896	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A	0	0	1291985542	1855037	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A	0	0	1291985542	1841	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1841	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1841	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1764	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1849	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A	0	0	1291985542	1891941	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A	0	0	1291985542	1881	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1881	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1881	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1799	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1891	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A	0	0	1291985542	1920018	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A	0	0	1291985542	1925	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1925	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1925	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1848	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1933	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A	0	0	1291985542	1857026	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A	0	0	1291985542	1843	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1843	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1843	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1765	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1851	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A	0	0	1291985542	1857615	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A	0	0	1291985542	1851	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1851	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1851	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1770	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1860	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A	0	0	1291985542	1890685	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A	0	0	1291985542	1885	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1885	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1885	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1806	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1895	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A	0	0	1291985542	1466085	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A	0	0	1291985542	1419	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1419	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1419	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1338	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1427	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A	0	0	1291985542	1434070	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A	0	0	1291985542	1399	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1399	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1399	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1320	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1409	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A	0	0	1291985542	1435751	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A	0	0	1291985542	1408	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1408	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1408	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1331	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1419	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A	0	0	1291985542	1391703	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A	0	0	1291985542	1367	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1367	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1367	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1285	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1375	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A	0	0	1291985542	6843741	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A	0	0	1291985542	7010	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	7010	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	7010	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	6928	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	7020	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A	0	0	1291985542	6951330	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A	0	0	1291985542	7163	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	7163	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	7163	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	7080	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	7172	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A	0	0	1291985542	6739152	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A	0	0	1291985542	6996	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	6996	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	6996	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	6910	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	7005	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A	0	0	1291985542	6814107	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A	0	0	1291985542	7072	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	7072	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	7072	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	6987	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	7082	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A	0	0	1291985542	7399554	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A	0	0	1291985542	7544	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	7544	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	7544	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	7461	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	7554	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A	0	0	1291985542	7468834	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A	0	0	1291985542	7638	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	7638	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	7638	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	7553	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	7649	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A	0	0	1291985542	7234018	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A	0	0	1291985542	7461	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	7461	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	7461	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	7372	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	7469	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A	0	0	1291985542	7394827	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A	0	0	1291985542	7589	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	7589	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	7589	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	7503	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	7597	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A	0	0	1291985542	1951074	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A	0	0	1291985542	1963	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1291985542	1963	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	7724930	1963	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	7724930	1884	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1291985542	1974	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A	0	0	1291985542	1157383	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A	0	0	7724930	7068093	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A	0	0	1291985542	1140	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A	0	0	1291985542	1291543112	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	1028	0	10
Category 0	1028	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	1028	0	10
Severity 0	1028	0	10

	NUMBER	PERCENT
Total Number	1028	100.00
Uncovered	6	0.58
Success	1022	99.42
Failure	0	0.00
Incomplete	1	0.10
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	0	0.00
All Matches	10	100.00
First Matches	10	100.00