Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T8,T9,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T2,T15
1	0	Covered	T8,T9,T10
1	1	Covered	T4,T2,T15

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	212698	0	0
SrcPulseCheck_M	2147483647	215767	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	212698
T2	71478	2
T3	360015	2
T7	189375	0
T8	347190	0
T12	0	2
T14	53638	0
T15	55891	2
T16	220080	14
T17	146703	0
T18	183981	0
T27	244076	0
T30	284220	0
T31	0	12
T32	0	16
T33	0	2
T34	606184	1
T35	0	15
T36	0	6
T50	323958	0
T51	211386	0
T60	312186	2
T61	97362	2
T62	0	2
T63	0	2
T64	0	16
T65	0	12
T66	0	16
T67	0	18
T68	0	16
T69	0	14
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	215767
T2	71478	2
T3	360015	2
T7	189375	0
T8	347190	0
T12	0	2
T14	53638	0
T15	55891	2
T16	220080	14
T17	146703	0
T18	183981	0
T27	244076	0
T30	284220	0
T31	0	12
T32	0	16
T33	0	2
T34	5270	1
T35	0	15
T36	0	6
T50	982	0
T51	640	0
T60	312186	2
T61	97362	2
T62	0	2
T63	0	2
T64	0	16
T65	0	12
T66	0	16
T67	0	18
T68	0	16
T69	0	14
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T2 T15

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T22,T24,T355

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T2,T15
1	0	Covered	T22,T24,T355
1	1	Covered	T4,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1884	0	0
SrcPulseCheck_M	1291985542	1974	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1884
T1	865	0
T2	506	1
T3	0	1
T4	599	1
T5	429	0
T6	430	0
T12	0	1
T14	426	0
T15	462	1
T19	505	0
T20	418	0
T21	406	0
T33	0	1
T60	0	1
T61	0	1
T81	0	1
T82	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1974
T1	45562	0
T2	70972	1
T3	0	1
T4	17981	1
T5	34399	0
T6	53876	0
T12	0	1
T14	53212	0
T15	55429	1
T19	60663	0
T20	37665	0
T21	50837	0
T33	0	1
T60	0	1
T61	0	1
T81	0	1
T82	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T22,T24,T355

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T2,T15
1	0	Covered	T22,T24,T355
1	1	Covered	T4,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1963	0	0
SrcPulseCheck_M	7724930	1963	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1963
T1	45562	0
T2	70972	1
T3	0	1
T4	17981	1
T5	34399	0
T6	53876	0
T12	0	1
T14	53212	0
T15	55429	1
T19	60663	0
T20	37665	0
T21	50837	0
T33	0	1
T60	0	1
T61	0	1
T81	0	1
T82	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1963
T1	865	0
T2	506	1
T3	0	1
T4	599	1
T5	429	0
T6	430	0
T12	0	1
T14	426	0
T15	462	1
T19	505	0
T20	418	0
T21	406	0
T33	0	1
T60	0	1
T61	0	1
T81	0	1
T82	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T8 T9 T10

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T10,T75

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T10,T75
1	1	Covered	T8,T9,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1050	0	0
SrcPulseCheck_M	1291985542	1143	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1050
T8	1193	3
T9	0	1
T10	0	3
T27	496	0
T30	524	0
T33	462	0
T60	431	0
T61	438	0
T64	0	1
T65	0	1
T75	0	2
T78	4414	0
T79	528	0
T80	510	0
T81	679	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1143
T8	114537	3
T9	0	1
T10	0	3
T27	121542	0
T30	141586	0
T33	222078	0
T60	103631	0
T61	48243	0
T64	0	1
T65	0	1
T75	0	2
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T10,T75

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T10,T75
1	1	Covered	T8,T9,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1133	0	0
SrcPulseCheck_M	7724930	1133	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1133
T8	114537	3
T9	0	1
T10	0	3
T27	121542	0
T30	141586	0
T33	222078	0
T60	103631	0
T61	48243	0
T64	0	1
T65	0	1
T75	0	2
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1133
T8	1193	3
T9	0	1
T10	0	3
T27	496	0
T30	524	0
T33	462	0
T60	431	0
T61	438	0
T64	0	1
T65	0	1
T75	0	2
T78	4414	0
T79	528	0
T80	510	0
T81	679	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T8 T9 T10

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T10,T75

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T10,T75
1	1	Covered	T8,T9,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1048	0	0
SrcPulseCheck_M	1291985542	1140	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1048
T8	1193	3
T9	0	1
T10	0	3
T27	496	0
T30	524	0
T33	462	0
T60	431	0
T61	438	0
T64	0	1
T65	0	1
T75	0	2
T78	4414	0
T79	528	0
T80	510	0
T81	679	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1140
T8	114537	3
T9	0	1
T10	0	3
T27	121542	0
T30	141586	0
T33	222078	0
T60	103631	0
T61	48243	0
T64	0	1
T65	0	1
T75	0	2
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T10,T75

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T10,T75
1	1	Covered	T8,T9,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1128	0	0
SrcPulseCheck_M	7724930	1128	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1128
T8	114537	3
T9	0	1
T10	0	3
T27	121542	0
T30	141586	0
T33	222078	0
T60	103631	0
T61	48243	0
T64	0	1
T65	0	1
T75	0	2
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1128
T8	1193	3
T9	0	1
T10	0	3
T27	496	0
T30	524	0
T33	462	0
T60	431	0
T61	438	0
T64	0	1
T65	0	1
T75	0	2
T78	4414	0
T79	528	0
T80	510	0
T81	679	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T8 T9 T10

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T10,T75

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T10,T75
1	1	Covered	T8,T9,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1065	0	0
SrcPulseCheck_M	1291985542	1149	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1065
T8	1193	3
T9	0	1
T10	0	3
T27	496	0
T30	524	0
T33	462	0
T60	431	0
T61	438	0
T64	0	1
T65	0	1
T75	0	2
T78	4414	0
T79	528	0
T80	510	0
T81	679	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1149
T8	114537	3
T9	0	1
T10	0	3
T27	121542	0
T30	141586	0
T33	222078	0
T60	103631	0
T61	48243	0
T64	0	1
T65	0	1
T75	0	2
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T10,T75

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T10,T75
1	1	Covered	T8,T9,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1141	0	0
SrcPulseCheck_M	7724930	1141	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1141
T8	114537	3
T9	0	1
T10	0	3
T27	121542	0
T30	141586	0
T33	222078	0
T60	103631	0
T61	48243	0
T64	0	1
T65	0	1
T75	0	2
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1141
T8	1193	3
T9	0	1
T10	0	3
T27	496	0
T30	524	0
T33	462	0
T60	431	0
T61	438	0
T64	0	1
T65	0	1
T75	0	2
T78	4414	0
T79	528	0
T80	510	0
T81	679	0
T83	0	1
T84	0	1
T85	0	1
T86	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T8 T9 T10

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1085	0	0
SrcPulseCheck_M	1291985542	1173	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1085
T8	1193	2
T9	0	2
T10	0	2
T27	496	0
T30	524	0
T33	462	0
T35	0	4
T53	0	4
T60	431	0
T61	438	0
T64	0	2
T70	0	2
T75	0	2
T76	0	4
T77	0	2
T78	4414	0
T79	528	0
T80	510	0
T81	679	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1173
T8	114537	2
T9	0	2
T10	0	2
T27	121542	0
T30	141586	0
T33	222078	0
T35	0	4
T53	0	4
T60	103631	0
T61	48243	0
T64	0	2
T70	0	2
T75	0	2
T76	0	4
T77	0	2
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1164	0	0
SrcPulseCheck_M	7724930	1164	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1164
T8	114537	2
T9	0	2
T10	0	2
T27	121542	0
T30	141586	0
T33	222078	0
T35	0	4
T53	0	4
T60	103631	0
T61	48243	0
T64	0	2
T70	0	2
T75	0	2
T76	0	4
T77	0	2
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1164
T8	1193	2
T9	0	2
T10	0	2
T27	496	0
T30	524	0
T33	462	0
T35	0	4
T53	0	4
T60	431	0
T61	438	0
T64	0	2
T70	0	2
T75	0	2
T76	0	4
T77	0	2
T78	4414	0
T79	528	0
T80	510	0
T81	679	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T8 T9 T10

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10
1	1	Covered	T76,T42,T163

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T8,T9,T10
1	0	Covered	T76,T42,T163
1	1	Covered	T8,T9,T10

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	908	0	0
SrcPulseCheck_M	1291985542	993	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	908
T8	1193	1
T9	0	1
T10	0	1
T27	496	0
T30	524	0
T33	462	0
T36	0	4
T56	0	1
T60	431	0
T61	438	0
T64	0	1
T70	0	1
T75	0	1
T76	0	2
T77	0	1
T78	4414	0
T79	528	0
T80	510	0
T81	679	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	993
T8	114537	1
T9	0	1
T10	0	1
T27	121542	0
T30	141586	0
T33	222078	0
T35	0	1
T36	0	4
T60	103631	0
T61	48243	0
T64	0	1
T70	0	1
T75	0	1
T76	0	2
T77	0	1
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T27 T28 T29

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T27,T28,T29
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T27,T28,T29
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	2258	0	0
SrcPulseCheck_M	1291985542	2343	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	2258
T9	571	0
T27	496	20
T28	494	20
T29	0	20
T33	462	0
T78	4414	0
T79	528	0
T80	510	0
T81	679	0
T87	0	20
T88	0	20
T89	0	20
T90	0	20
T91	0	20
T92	0	20
T93	0	20
T94	422	0
T95	408	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	2343
T9	225448	0
T27	121542	20
T28	242197	20
T29	0	20
T33	222078	0
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0
T87	0	20
T88	0	20
T89	0	20
T90	0	20
T91	0	20
T92	0	20
T93	0	20
T94	202626	0
T95	98047	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T27,T28,T29
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T27,T28,T29
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	2333	0	0
SrcPulseCheck_M	7724930	2333	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	2333
T9	225448	0
T27	121542	20
T28	242197	20
T29	0	20
T33	222078	0
T78	463517	0
T79	31721	0
T80	45874	0
T81	169900	0
T87	0	20
T88	0	20
T89	0	20
T90	0	20
T91	0	20
T92	0	20
T93	0	20
T94	202626	0
T95	98047	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	2333
T9	571	0
T27	496	20
T28	494	20
T29	0	20
T33	462	0
T78	4414	0
T79	528	0
T80	510	0
T81	679	0
T87	0	20
T88	0	20
T89	0	20
T90	0	20
T91	0	20
T92	0	20
T93	0	20
T94	422	0
T95	408	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T19 T18 T30

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T19,T18,T30
1	0	Covered	T19,T18,T30
1	1	Covered	T19,T18,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T19,T18,T30
1	0	Covered	T19,T18,T30
1	1	Covered	T19,T18,T30

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	4148	0	0
SrcPulseCheck_M	1291985542	4243	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	4148
T1	865	0
T2	506	0
T14	426	0
T15	462	0
T16	726	0
T17	404	0
T18	507	20
T19	505	20
T20	418	0
T21	406	0
T27	0	1
T28	0	1
T29	0	1
T30	0	20
T79	0	20
T80	0	20
T87	0	1
T96	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	4243
T1	45562	0
T2	70972	0
T14	53212	0
T15	55429	0
T16	72634	0
T17	48497	0
T18	60820	20
T19	60663	20
T20	37665	0
T21	50837	0
T27	0	1
T28	0	1
T29	0	1
T30	0	20
T79	0	20
T80	0	20
T87	0	1
T96	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T19,T18,T30
1	0	Covered	T19,T18,T30
1	1	Covered	T19,T18,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T19,T18,T30
1	0	Covered	T19,T18,T30
1	1	Covered	T19,T18,T30

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	4227	0	0
SrcPulseCheck_M	7724930	4227	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	4227
T1	45562	0
T2	70972	0
T14	53212	0
T15	55429	0
T16	72634	0
T17	48497	0
T18	60820	20
T19	60663	20
T20	37665	0
T21	50837	0
T27	0	1
T28	0	1
T29	0	1
T30	0	20
T79	0	20
T80	0	20
T87	0	1
T96	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	4227
T1	865	0
T2	506	0
T14	426	0
T15	462	0
T16	726	0
T17	404	0
T18	507	20
T19	505	20
T20	418	0
T21	406	0
T27	0	1
T28	0	1
T29	0	1
T30	0	20
T79	0	20
T80	0	20
T87	0	1
T96	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T19 T2

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T19,T2
1	0	Covered	T4,T19,T2
1	1	Covered	T19,T18,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T19,T2
1	0	Covered	T19,T18,T30
1	1	Covered	T4,T19,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	5133	0	0
SrcPulseCheck_M	1291985542	5227	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	5133
T1	865	0
T2	506	1
T3	0	1
T4	599	1
T5	429	0
T6	430	0
T14	426	0
T15	462	1
T18	0	20
T19	505	20
T20	418	0
T21	406	0
T27	0	1
T30	0	20
T60	0	1
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	5227
T1	45562	0
T2	70972	1
T3	0	1
T4	17981	1
T5	34399	0
T6	53876	0
T14	53212	0
T15	55429	1
T18	0	20
T19	60663	20
T20	37665	0
T21	50837	0
T27	0	1
T30	0	20
T60	0	1
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T19,T2
1	0	Covered	T4,T19,T2
1	1	Covered	T19,T18,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T19,T2
1	0	Covered	T19,T18,T30
1	1	Covered	T4,T19,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	5212	0	0
SrcPulseCheck_M	7724930	5212	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	5212
T1	45562	0
T2	70972	1
T3	0	1
T4	17981	1
T5	34399	0
T6	53876	0
T14	53212	0
T15	55429	1
T18	0	20
T19	60663	20
T20	37665	0
T21	50837	0
T27	0	1
T30	0	20
T60	0	1
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	5212
T1	865	0
T2	506	1
T3	0	1
T4	599	1
T5	429	0
T6	430	0
T14	426	0
T15	462	1
T18	0	20
T19	505	20
T20	418	0
T21	406	0
T27	0	1
T30	0	20
T60	0	1
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T19 T18 T30

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T19,T18,T30
1	0	Covered	T19,T18,T30
1	1	Covered	T19,T18,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T19,T18,T30
1	0	Covered	T19,T18,T30
1	1	Covered	T19,T18,T30

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	4075	0	0
SrcPulseCheck_M	1291985542	4169	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	4075
T1	865	0
T2	506	0
T14	426	0
T15	462	0
T16	726	0
T17	404	0
T18	507	20
T19	505	20
T20	418	0
T21	406	0
T30	0	20
T79	0	20
T80	0	20
T96	0	20
T97	0	20
T98	0	20
T99	0	20
T100	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	4169
T1	45562	0
T2	70972	0
T14	53212	0
T15	55429	0
T16	72634	0
T17	48497	0
T18	60820	20
T19	60663	20
T20	37665	0
T21	50837	0
T30	0	20
T79	0	20
T80	0	20
T96	0	20
T97	0	20
T98	0	20
T99	0	20
T100	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T19,T18,T30
1	0	Covered	T19,T18,T30
1	1	Covered	T19,T18,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T19,T18,T30
1	0	Covered	T19,T18,T30
1	1	Covered	T19,T18,T30

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	4154	0	0
SrcPulseCheck_M	7724930	4154	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	4154
T1	45562	0
T2	70972	0
T14	53212	0
T15	55429	0
T16	72634	0
T17	48497	0
T18	60820	20
T19	60663	20
T20	37665	0
T21	50837	0
T30	0	20
T79	0	20
T80	0	20
T96	0	20
T97	0	20
T98	0	20
T99	0	20
T100	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	4154
T1	865	0
T2	506	0
T14	426	0
T15	462	0
T16	726	0
T17	404	0
T18	507	20
T19	505	20
T20	418	0
T21	406	0
T30	0	20
T79	0	20
T80	0	20
T96	0	20
T97	0	20
T98	0	20
T99	0	20
T100	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T7 T11

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T35,T53,T22
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1059	0	0
SrcPulseCheck_M	1291985542	1149	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1059
T1	865	1
T2	506	0
T3	487	0
T7	830	1
T8	1193	0
T11	0	1
T13	0	1
T14	426	0
T15	462	0
T16	726	0
T17	404	0
T18	507	0
T35	0	28
T47	0	1
T48	0	1
T49	0	1
T50	0	1
T51	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1149
T1	45562	1
T2	70972	0
T3	119518	0
T7	62295	1
T8	114537	0
T11	0	1
T13	0	1
T14	53212	0
T15	55429	0
T16	72634	0
T17	48497	0
T18	60820	0
T35	0	28
T47	0	1
T48	0	1
T49	0	1
T50	0	1
T51	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T35,T53,T22
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1140	0	0
SrcPulseCheck_M	7724930	1140	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1140
T1	45562	1
T2	70972	0
T3	119518	0
T7	62295	1
T8	114537	0
T11	0	1
T13	0	1
T14	53212	0
T15	55429	0
T16	72634	0
T17	48497	0
T18	60820	0
T35	0	28
T47	0	1
T48	0	1
T49	0	1
T50	0	1
T51	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1140
T1	865	1
T2	506	0
T3	487	0
T7	830	1
T8	1193	0
T11	0	1
T13	0	1
T14	426	0
T15	462	0
T16	726	0
T17	404	0
T18	507	0
T35	0	28
T47	0	1
T48	0	1
T49	0	1
T50	0	1
T51	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T15

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T15
1	0	Covered	T35,T53,T22
1	1	Covered	T1,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1886	0	0
SrcPulseCheck_M	1291985542	1974	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1886
T1	865	1
T2	506	1
T3	487	1
T7	830	1
T8	1193	0
T11	0	1
T12	0	1
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T60	0	1
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1974
T1	45562	1
T2	70972	1
T3	119518	1
T7	62295	1
T8	114537	0
T11	0	1
T12	0	1
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T60	0	1
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T15
1	0	Covered	T35,T53,T22
1	1	Covered	T1,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1963	0	0
SrcPulseCheck_M	7724930	1963	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1963
T1	45562	1
T2	70972	1
T3	119518	1
T7	62295	1
T8	114537	0
T11	0	1
T12	0	1
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T60	0	1
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1963
T1	865	1
T2	506	1
T3	487	1
T7	830	1
T8	1193	0
T11	0	1
T12	0	1
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T60	0	1
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T16 T31 T32

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T16,T31,T32
1	0	Covered	T16,T31,T32
1	1	Covered	T16,T31,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T16,T31,T32
1	0	Covered	T16,T31,T32
1	1	Covered	T16,T31,T32

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1277	0	0
SrcPulseCheck_M	1291985542	1363	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1277
T3	487	0
T7	830	0
T8	1193	0
T16	726	4
T17	404	0
T18	507	0
T27	496	0
T30	524	0
T31	0	3
T32	0	5
T35	0	2
T60	431	0
T61	438	0
T64	0	4
T65	0	4
T66	0	5
T67	0	6
T68	0	5
T69	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1363
T3	119518	0
T7	62295	0
T8	114537	0
T16	72634	4
T17	48497	0
T18	60820	0
T27	121542	0
T30	141586	0
T31	0	3
T32	0	5
T35	0	2
T60	103631	0
T61	48243	0
T64	0	4
T65	0	4
T66	0	5
T67	0	6
T68	0	5
T69	0	4

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T16,T31,T32
1	0	Covered	T16,T31,T32
1	1	Covered	T16,T31,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T16,T31,T32
1	0	Covered	T16,T31,T32
1	1	Covered	T16,T31,T32

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1353	0	0
SrcPulseCheck_M	7724930	1353	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1353
T3	119518	0
T7	62295	0
T8	114537	0
T16	72634	4
T17	48497	0
T18	60820	0
T27	121542	0
T30	141586	0
T31	0	3
T32	0	5
T35	0	2
T60	103631	0
T61	48243	0
T64	0	4
T65	0	4
T66	0	5
T67	0	6
T68	0	5
T69	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1353
T3	487	0
T7	830	0
T8	1193	0
T16	726	4
T17	404	0
T18	507	0
T27	496	0
T30	524	0
T31	0	3
T32	0	5
T35	0	2
T60	431	0
T61	438	0
T64	0	4
T65	0	4
T66	0	5
T67	0	6
T68	0	5
T69	0	4

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T16 T31 T32

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T16,T31,T32
1	0	Covered	T16,T31,T32
1	1	Covered	T16,T31,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T16,T31,T32
1	0	Covered	T16,T31,T32
1	1	Covered	T16,T31,T32

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1144	0	0
SrcPulseCheck_M	1291985542	1234	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1144
T3	487	0
T7	830	0
T8	1193	0
T16	726	3
T17	404	0
T18	507	0
T27	496	0
T30	524	0
T31	0	3
T32	0	3
T35	0	1
T60	431	0
T61	438	0
T64	0	3
T65	0	2
T66	0	3
T67	0	3
T68	0	3
T69	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1234
T3	119518	0
T7	62295	0
T8	114537	0
T16	72634	3
T17	48497	0
T18	60820	0
T27	121542	0
T30	141586	0
T31	0	3
T32	0	3
T35	0	1
T60	103631	0
T61	48243	0
T64	0	3
T65	0	2
T66	0	3
T67	0	3
T68	0	3
T69	0	3

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T16,T31,T32
1	0	Covered	T16,T31,T32
1	1	Covered	T16,T31,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T16,T31,T32
1	0	Covered	T16,T31,T32
1	1	Covered	T16,T31,T32

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1224	0	0
SrcPulseCheck_M	7724930	1224	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1224
T3	119518	0
T7	62295	0
T8	114537	0
T16	72634	3
T17	48497	0
T18	60820	0
T27	121542	0
T30	141586	0
T31	0	3
T32	0	3
T35	0	1
T60	103631	0
T61	48243	0
T64	0	3
T65	0	2
T66	0	3
T67	0	3
T68	0	3
T69	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1224
T3	487	0
T7	830	0
T8	1193	0
T16	726	3
T17	404	0
T18	507	0
T27	496	0
T30	524	0
T31	0	3
T32	0	3
T35	0	1
T60	431	0
T61	438	0
T64	0	3
T65	0	2
T66	0	3
T67	0	3
T68	0	3
T69	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T2 T15 T33

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T33
1	0	Covered	T2,T15,T33
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T33
1	0	Covered	T34,T35,T36
1	1	Covered	T2,T15,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	6928	0	0
SrcPulseCheck_M	1291985542	7020	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	6928
T2	506	1
T3	487	0
T7	830	0
T8	1193	0
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T34	0	51
T35	0	11
T36	0	89
T53	0	11
T59	0	51
T60	431	0
T62	0	1
T101	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	7020
T2	70972	1
T3	119518	0
T7	62295	0
T8	114537	0
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T34	0	51
T35	0	11
T36	0	89
T53	0	11
T59	0	51
T60	103631	0
T62	0	1
T101	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T33
1	0	Covered	T2,T15,T33
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T33
1	0	Covered	T34,T35,T36
1	1	Covered	T2,T15,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	7010	0	0
SrcPulseCheck_M	7724930	7010	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	7010
T2	70972	1
T3	119518	0
T7	62295	0
T8	114537	0
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T34	0	51
T35	0	11
T36	0	89
T53	0	11
T59	0	51
T60	103631	0
T62	0	1
T101	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	7010
T2	506	1
T3	487	0
T7	830	0
T8	1193	0
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T34	0	51
T35	0	11
T36	0	89
T53	0	11
T59	0	51
T60	431	0
T62	0	1
T101	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	7080	0	0
SrcPulseCheck_M	1291985542	7172	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	7080
T34	5270	51
T35	0	11
T36	0	78
T42	0	80
T50	982	0
T51	640	0
T53	0	11
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	7172
T34	606184	51
T35	0	11
T36	0	78
T42	0	80
T50	323958	0
T51	211386	0
T53	0	11
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	7163	0	0
SrcPulseCheck_M	7724930	7163	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	7163
T34	606184	51
T35	0	11
T36	0	78
T42	0	80
T50	323958	0
T51	211386	0
T53	0	11
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	7163
T34	5270	51
T35	0	11
T36	0	78
T42	0	80
T50	982	0
T51	640	0
T53	0	11
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	6910	0	0
SrcPulseCheck_M	1291985542	7005	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	6910
T34	5270	51
T35	0	11
T36	0	68
T42	0	68
T50	982	0
T51	640	0
T53	0	11
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	7005
T34	606184	51
T35	0	11
T36	0	68
T42	0	68
T50	323958	0
T51	211386	0
T53	0	11
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	6996	0	0
SrcPulseCheck_M	7724930	6996	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	6996
T34	606184	51
T35	0	11
T36	0	68
T42	0	68
T50	323958	0
T51	211386	0
T53	0	11
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	6996
T34	5270	51
T35	0	11
T36	0	68
T42	0	68
T50	982	0
T51	640	0
T53	0	11
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	6987	0	0
SrcPulseCheck_M	1291985542	7082	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	6987
T34	5270	51
T35	0	11
T36	0	68
T42	0	86
T50	982	0
T51	640	0
T53	0	11
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	7082
T34	606184	51
T35	0	11
T36	0	68
T42	0	86
T50	323958	0
T51	211386	0
T53	0	11
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	7072	0	0
SrcPulseCheck_M	7724930	7072	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	7072
T34	606184	51
T35	0	11
T36	0	68
T42	0	86
T50	323958	0
T51	211386	0
T53	0	11
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	7072
T34	5270	51
T35	0	11
T36	0	68
T42	0	86
T50	982	0
T51	640	0
T53	0	11
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T104	0	51
T105	0	51
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T2 T15 T33

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T33
1	0	Covered	T2,T15,T33
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T33
1	0	Covered	T35,T53,T22
1	1	Covered	T2,T15,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1338	0	0
SrcPulseCheck_M	1291985542	1427	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1338
T2	506	1
T3	487	0
T7	830	0
T8	1193	0
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T34	0	1
T35	0	9
T36	0	6
T53	0	9
T59	0	1
T60	431	0
T62	0	1
T101	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1427
T2	70972	1
T3	119518	0
T7	62295	0
T8	114537	0
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T34	0	1
T35	0	9
T36	0	6
T53	0	9
T59	0	1
T60	103631	0
T62	0	1
T101	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T33
1	0	Covered	T2,T15,T33
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T33
1	0	Covered	T35,T53,T22
1	1	Covered	T2,T15,T33

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1419	0	0
SrcPulseCheck_M	7724930	1419	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1419
T2	70972	1
T3	119518	0
T7	62295	0
T8	114537	0
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T34	0	1
T35	0	9
T36	0	6
T53	0	9
T59	0	1
T60	103631	0
T62	0	1
T101	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1419
T2	506	1
T3	487	0
T7	830	0
T8	1193	0
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T34	0	1
T35	0	9
T36	0	6
T53	0	9
T59	0	1
T60	431	0
T62	0	1
T101	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1320	0	0
SrcPulseCheck_M	1291985542	1409	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1320
T34	5270	1
T35	0	9
T36	0	6
T42	0	7
T50	982	0
T51	640	0
T53	0	9
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1409
T34	606184	1
T35	0	9
T36	0	6
T42	0	7
T50	323958	0
T51	211386	0
T53	0	9
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1399	0	0
SrcPulseCheck_M	7724930	1399	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1399
T34	606184	1
T35	0	9
T36	0	6
T42	0	7
T50	323958	0
T51	211386	0
T53	0	9
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1399
T34	5270	1
T35	0	9
T36	0	6
T42	0	7
T50	982	0
T51	640	0
T53	0	9
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1331	0	0
SrcPulseCheck_M	1291985542	1419	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1331
T34	5270	1
T35	0	9
T36	0	6
T42	0	7
T50	982	0
T51	640	0
T53	0	9
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1419
T34	606184	1
T35	0	9
T36	0	6
T42	0	7
T50	323958	0
T51	211386	0
T53	0	9
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1408	0	0
SrcPulseCheck_M	7724930	1408	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1408
T34	606184	1
T35	0	9
T36	0	6
T42	0	7
T50	323958	0
T51	211386	0
T53	0	9
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1408
T34	5270	1
T35	0	9
T36	0	6
T42	0	7
T50	982	0
T51	640	0
T53	0	9
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1285	0	0
SrcPulseCheck_M	1291985542	1375	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1285
T34	5270	1
T35	0	9
T36	0	6
T42	0	7
T50	982	0
T51	640	0
T53	0	9
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1375
T34	606184	1
T35	0	9
T36	0	6
T42	0	7
T50	323958	0
T51	211386	0
T53	0	9
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1367	0	0
SrcPulseCheck_M	7724930	1367	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1367
T34	606184	1
T35	0	9
T36	0	6
T42	0	7
T50	323958	0
T51	211386	0
T53	0	9
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1367
T34	5270	1
T35	0	9
T36	0	6
T42	0	7
T50	982	0
T51	640	0
T53	0	9
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T104	0	1
T105	0	1
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T2 T15 T3

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T2,T15,T3
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T34,T35,T36
1	1	Covered	T2,T15,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	7461	0	0
SrcPulseCheck_M	1291985542	7554	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	7461
T2	506	1
T3	487	1
T7	830	0
T8	1193	0
T12	0	1
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T60	431	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	7554
T2	70972	1
T3	119518	1
T7	62295	0
T8	114537	0
T12	0	1
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T60	103631	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T2,T15,T3
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T34,T35,T36
1	1	Covered	T2,T15,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	7544	0	0
SrcPulseCheck_M	7724930	7544	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	7544
T2	70972	1
T3	119518	1
T7	62295	0
T8	114537	0
T12	0	1
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T60	103631	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	7544
T2	506	1
T3	487	1
T7	830	0
T8	1193	0
T12	0	1
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T60	431	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	7553	0	0
SrcPulseCheck_M	1291985542	7649	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	7553
T34	5270	51
T35	0	11
T36	0	78
T40	0	2
T50	982	0
T51	640	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	7649
T34	606184	51
T35	0	11
T36	0	78
T40	0	2
T50	323958	0
T51	211386	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	7638	0	0
SrcPulseCheck_M	7724930	7638	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	7638
T34	606184	51
T35	0	11
T36	0	78
T40	0	2
T50	323958	0
T51	211386	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	7638
T34	5270	51
T35	0	11
T36	0	78
T40	0	2
T50	982	0
T51	640	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	7372	0	0
SrcPulseCheck_M	1291985542	7469	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	7372
T34	5270	51
T35	0	11
T36	0	68
T40	0	2
T50	982	0
T51	640	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	7469
T34	606184	51
T35	0	11
T36	0	68
T40	0	2
T50	323958	0
T51	211386	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	7461	0	0
SrcPulseCheck_M	7724930	7461	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	7461
T34	606184	51
T35	0	11
T36	0	68
T40	0	2
T50	323958	0
T51	211386	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	7461
T34	5270	51
T35	0	11
T36	0	68
T40	0	2
T50	982	0
T51	640	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	7503	0	0
SrcPulseCheck_M	1291985542	7597	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	7503
T34	5270	51
T35	0	11
T36	0	68
T40	0	2
T50	982	0
T51	640	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	7597
T34	606184	51
T35	0	11
T36	0	68
T40	0	2
T50	323958	0
T51	211386	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	7589	0	0
SrcPulseCheck_M	7724930	7589	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	7589
T34	606184	51
T35	0	11
T36	0	68
T40	0	2
T50	323958	0
T51	211386	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	51
T103	0	51
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	7589
T34	5270	51
T35	0	11
T36	0	68
T40	0	2
T50	982	0
T51	640	0
T53	0	11
T56	0	4
T57	0	3
T59	0	51
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	51
T103	0	51
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T2 T15 T3

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T2,T15,T3
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T35,T53,T22
1	1	Covered	T2,T15,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1831	0	0
SrcPulseCheck_M	1291985542	1918	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1831
T2	506	1
T3	487	1
T7	830	0
T8	1193	0
T12	0	1
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T60	431	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1918
T2	70972	1
T3	119518	1
T7	62295	0
T8	114537	0
T12	0	1
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T60	103631	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T2,T15,T3
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T35,T53,T22
1	1	Covered	T2,T15,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1908	0	0
SrcPulseCheck_M	7724930	1908	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1908
T2	70972	1
T3	119518	1
T7	62295	0
T8	114537	0
T12	0	1
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T60	103631	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1908
T2	506	1
T3	487	1
T7	830	0
T8	1193	0
T12	0	1
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T60	431	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1805	0	0
SrcPulseCheck_M	1291985542	1896	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1805
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1896
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1887	0	0
SrcPulseCheck_M	7724930	1887	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1887
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1887
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1764	0	0
SrcPulseCheck_M	1291985542	1849	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1764
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1849
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1841	0	0
SrcPulseCheck_M	7724930	1841	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1841
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1841
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1799	0	0
SrcPulseCheck_M	1291985542	1891	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1799
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1891
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1881	0	0
SrcPulseCheck_M	7724930	1881	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1881
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1881
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T2 T15 T3

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T2,T15,T3
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T35,T53,T22
1	1	Covered	T2,T15,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1848	0	0
SrcPulseCheck_M	1291985542	1933	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1848
T2	506	1
T3	487	1
T7	830	0
T8	1193	0
T12	0	1
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T60	431	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1933
T2	70972	1
T3	119518	1
T7	62295	0
T8	114537	0
T12	0	1
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T60	103631	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T2,T15,T3
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T15,T3
1	0	Covered	T35,T53,T22
1	1	Covered	T2,T15,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1925	0	0
SrcPulseCheck_M	7724930	1925	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1925
T2	70972	1
T3	119518	1
T7	62295	0
T8	114537	0
T12	0	1
T14	53212	0
T15	55429	1
T16	72634	0
T17	48497	0
T18	60820	0
T33	0	1
T60	103631	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1925
T2	506	1
T3	487	1
T7	830	0
T8	1193	0
T12	0	1
T14	426	0
T15	462	1
T16	726	0
T17	404	0
T18	507	0
T33	0	1
T60	431	1
T61	0	1
T62	0	1
T63	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1765	0	0
SrcPulseCheck_M	1291985542	1851	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1765
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1851
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1843	0	0
SrcPulseCheck_M	7724930	1843	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1843
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1843
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1770	0	0
SrcPulseCheck_M	1291985542	1860	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1770
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1860
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1851	0	0
SrcPulseCheck_M	7724930	1851	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1851
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1851
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T34 T35 T36

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7724930	1806	0	0
SrcPulseCheck_M	1291985542	1895	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7724930	1806
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1291985542	1895
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00



30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T35,T53,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T53,T22
1	1	Covered	T34,T35,T36

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1291985542	1885	0	0
SrcPulseCheck_M	7724930	1885	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1291985542	1885
T34	606184	1
T35	0	9
T36	0	6
T40	0	2
T50	323958	0
T51	211386	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	58923	0
T71	200100	0
T72	55835	0
T73	51011	0
T74	248214	0
T102	0	1
T103	0	1
T106	136338	0
T107	816898	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7724930	1885
T34	5270	1
T35	0	9
T36	0	6
T40	0	2
T50	982	0
T51	640	0
T53	0	9
T56	0	4
T57	0	3
T59	0	1
T70	1176	0
T71	417	0
T72	1861	0
T73	408	0
T74	522	0
T102	0	1
T103	0	1
T106	556	0
T107	1649	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_lid_debounce_ctl_cdc