Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.34	96.34	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	96.34	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.34	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	3	59	95.16

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	3	28	90.32	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1618

1

T36

17

T56

5

T40

1

auto[1]

589

1

T36

7

T56

8

T57

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1676

1

T36

22

T56

9

T57

2

auto[1]

531

1

T36

2

T56

4

T40

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1672

1

T36

23

T56

5

T41

6

auto[1]

535

1

T36

1

T56

8

T57

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1746

1

T36

18

T56

3

T57

2

auto[1]

461

1

T36

6

T56

10

T40

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2058

1

T36

23

T56

13

T57

2

auto[1]

149

1

T36

1

T42

14

T130

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2001

1

T36

18

T56

13

T57

2

auto[1]

206

1

T36

6

T42

4

T130

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2012

1

T36

17

T56

13

T57

2

auto[1]

195

1

T36

7

T42

6

T130

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1968

1

T36

22

T56

13

T57

2

auto[1]

239

1

T36

2

T42

7

T118

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2038

1

T36

23

T56

13

T57

2

auto[1]

169

1

T36

1

T42

5

T280

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1697

1

T36

17

T56

8

T57

2

auto[1]

510

1

T36

7

T56

5

T41

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	3	28	90.32	3
Automatically Generated Cross Bins	31	3	28	90.32	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	742	1			T56	13		T57	2		T40	1
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	39	1			T42	10		T224	1		T134	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	39	1			T148	4		T391	9		T392	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	7	1			T281	4		T393	1		T394	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	90	1			T118	4		T285	3		T119	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	15	1			T236	2		T395	3		T396	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	48	1			T42	5		T391	4		T397	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T283	3		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	67	1			T36	5		T398	2		T399	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	14	1			T400	2		T401	2		T402	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T397	1		T382	2		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	5	1			T403	2		T404	3		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	29	1			T36	2		T42	2		T405	9
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	7	1			T119	2		T406	5		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T403	1		T407	1		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	86	1			T36	5		T280	14		T391	8
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	6	1			T134	1		T408	2		T409	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	7	1			T405	2		T406	5		-	-
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	20	1			T36	1		T403	4		T410	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	7	1			T404	2		T411	5		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	4	1			T380	1		T412	1		T413	2
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	9	1			T280	5		T132	4		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	4	1			T132	4		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	33	1			T280	6		T285	1		T380	3
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	10	1			T42	4		T130	2		T409	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T410	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	8	1			T281	2		T411	6		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	5	1			T280	3		T413	1		T384	1

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

129

1

T280

5

T380

3

T414

24

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

107

1

T36

5

T130

2

T133

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

80

1

T280

3

T135

1

T375

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

79

1

T42

4

T302

7

T280

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

50

1

T36

5

T45

6

T308

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T280

6

T285

1

T135

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T56

4

T114

2

T43

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

100

1

T58

11

T132

8

T371

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

77

1

T57

2

T45

8

T118

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

31

1

T312

1

T285

3

T286

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T46

1

T133

5

T370

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T36

1

T56

5

T154

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T43

3

T391

9

T408

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

22

1

T134

1

T370

2

T415

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T46

1

T133

3

T375

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

117

1

T302

8

T286

8

T373

13

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

49

1

T42

5

T397

2

T373

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

24

1

T42

2

T312

1

T119

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T36

2

T41

1

T45

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

21

1

T41

4

T46

3

T286

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T44

4

T46

2

T298

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

31

1

T41

1

T42

10

T141

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T56

1

T43

1

T370

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T224

1

T371

3

T416

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T56

3

T41

2

T137

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

31

1

T44

2

T395

7

T417

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T415

1

T142

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

35

1

T40

1

T134

1

T281

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T418

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

20

1

T45

1

T417

2

T287

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T58

1

T419

1

T379

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded