Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

698

1

T19

10

T18

10

T80

10

auto[1]

664

1

T19

10

T18

10

T80

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

323

1

T19

3

T18

6

T80

4

from_0to1

328

1

T19

4

T18

6

T80

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

676

1

T19

11

T18

7

T80

7

auto[1]

686

1

T19

9

T18

13

T80

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

669

1

T19

12

T18

12

T80

9

auto[1]

693

1

T19

8

T18

8

T80

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T18

1

T444

1

T77

1

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T19

1

T18

1

T444

2

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T19

1

T18

2

T99

1

auto[0]

from_1to0

auto[1]

auto[1]

46

1

T18

1

T80

2

T97

3

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T18

1

T97

2

T337

2

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T19

1

T80

1

T97

1

auto[0]

from_0to1

auto[1]

auto[0]

29

1

T18

1

T80

1

T97

1

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T18

1

T127

2

T77

2

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T18

1

T337

3

T86

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T97

1

T337

1

T181

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T80

1

T97

1

T99

1

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T19

1

T80

1

T99

1

auto[1]

from_0to1

auto[0]

auto[0]

37

1

T19

1

T86

2

T444

1

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T19

1

T18

1

T80

1

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T19

1

T18

2

T99

3

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T80

2

T99

1

T337

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

685

1

T19

8

T18

8

T80

11

auto[1]

677

1

T19

12

T18

12

T80

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

305

1

T19

4

T18

5

T80

6

from_0to1

309

1

T19

4

T18

5

T80

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678

1

T19

11

T18

10

T80

10

auto[1]

684

1

T19

9

T18

10

T80

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

667

1

T19

10

T18

6

T80

8

auto[1]

695

1

T19

10

T18

14

T80

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T97

1

T99

1

T445

2

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T19

2

T18

1

T80

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T80

1

T181

2

T86

2

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T18

2

T80

1

T337

1

auto[0]

from_0to1

auto[0]

auto[0]

45

1

T19

2

T18

1

T99

2

auto[0]

from_0to1

auto[0]

auto[1]

28

1

T86

1

T127

1

T292

1

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T97

1

T127

2

T446

1

auto[0]

from_0to1

auto[1]

auto[1]

39

1

T18

1

T80

1

T337

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T99

1

T337

2

T181

1

auto[1]

from_1to0

auto[0]

auto[1]

32

1

T80

2

T97

1

T86

1

auto[1]

from_1to0

auto[1]

auto[0]

36

1

T19

1

T18

1

T80

1

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T19

1

T18

1

T97

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T19

1

T80

1

T99

1

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T18

2

T80

2

T337

2

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T19

1

T80

1

T97

1

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T18

1

T97

1

T86

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

686

1

T19

12

T18

12

T80

10

auto[1]

676

1

T19

8

T18

8

T80

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

324

1

T19

6

T18

6

T80

5

from_0to1

329

1

T19

5

T18

6

T80

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

679

1

T19

9

T18

8

T80

10

auto[1]

683

1

T19

11

T18

12

T80

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

679

1

T19

12

T18

11

T80

9

auto[1]

683

1

T19

8

T18

9

T80

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T19

2

T99

1

T337

1

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T18

1

T80

1

T97

1

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T19

2

T18

3

T97

1

auto[0]

from_1to0

auto[1]

auto[1]

41

1

T97

1

T337

1

T181

1

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T19

1

T18

1

T80

1

auto[0]

from_0to1

auto[0]

auto[1]

41

1

T19

1

T18

1

T337

1

auto[0]

from_0to1

auto[1]

auto[0]

47

1

T97

2

T99

1

T127

1

auto[0]

from_0to1

auto[1]

auto[1]

46

1

T19

2

T18

2

T80

1

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T18

1

T80

1

T181

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T19

1

T337

1

T86

1

auto[1]

from_1to0

auto[1]

auto[0]

33

1

T19

1

T80

1

T97

2

auto[1]

from_1to0

auto[1]

auto[1]

51

1

T18

1

T80

2

T86

3

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T19

1

T18

1

T80

1

auto[1]

from_0to1

auto[0]

auto[1]

35

1

T80

1

T99

1

T337

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T18

1

T337

1

T181

2

auto[1]

from_0to1

auto[1]

auto[1]

37

1

T337

1

T86

1

T127

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

667

1

T19

11

T18

13

T80

13

auto[1]

695

1

T19

9

T18

7

T80

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

319

1

T19

5

T18

5

T80

6

from_0to1

316

1

T19

4

T18

5

T80

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

688

1

T19

9

T18

12

T80

10

auto[1]

674

1

T19

11

T18

8

T80

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

667

1

T19

13

T18

9

T80

10

auto[1]

695

1

T19

7

T18

11

T80

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T19

1

T80

1

T99

1

auto[0]

from_1to0

auto[0]

auto[1]

33

1

T18

2

T80

2

T97

1

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T19

2

T18

1

T80

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T18

1

T333

1

T181

1

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T19

1

T18

3

T97

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T18

1

T97

1

T99

1

auto[0]

from_0to1

auto[1]

auto[0]

35

1

T80

3

T181

1

T444

1

auto[0]

from_0to1

auto[1]

auto[1]

46

1

T19

1

T18

1

T97

1

auto[1]

from_1to0

auto[0]

auto[0]

32

1

T99

1

T337

1

T181

1

auto[1]

from_1to0

auto[0]

auto[1]

45

1

T19

1

T97

1

T337

1

auto[1]

from_1to0

auto[1]

auto[0]

44

1

T19

1

T18

1

T80

1

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T80

1

T97

1

T99

3

auto[1]

from_0to1

auto[0]

auto[0]

40

1

T19

1

T99

1

T445

1

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T80

2

T337

3

T86

1

auto[1]

from_0to1

auto[1]

auto[0]

32

1

T19

1

T97

1

T99

1

auto[1]

from_0to1

auto[1]

auto[1]

30

1

T86

2

T127

1

T77

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

701

1

T19

13

T18

10

T80

11

auto[1]

661

1

T19

7

T18

10

T80

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

320

1

T19

4

T18

6

T80

5

from_0to1

324

1

T19

3

T18

5

T80

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

718

1

T19

12

T18

9

T80

10

auto[1]

644

1

T19

8

T18

11

T80

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

677

1

T19

10

T18

12

T80

8

auto[1]

685

1

T19

10

T18

8

T80

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

45

1

T19

2

T337

1

T181

1

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T18

2

T97

2

T99

1

auto[0]

from_1to0

auto[1]

auto[0]

38

1

T99

1

T337

1

T181

1

auto[0]

from_1to0

auto[1]

auto[1]

48

1

T18

1

T80

2

T97

2

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T18

1

T99

1

T337

1

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T80

2

T97

3

T99

2

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T19

2

T18

1

T333

1

auto[0]

from_0to1

auto[1]

auto[1]

28

1

T19

1

T80

1

T99

1

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T19

1

T80

1

T97

1

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T19

1

T18

1

T337

1

auto[1]

from_1to0

auto[1]

auto[0]

34

1

T18

2

T337

1

T444

1

auto[1]

from_1to0

auto[1]

auto[1]

26

1

T80

2

T97

1

T99

1

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T18

1

T80

2

T97

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T337

2

T181

2

T86

1

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T18

1

T99

1

T181

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T18

1

T80

1

T97

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

649

1

T19

8

T18

9

T80

12

auto[1]

713

1

T19

12

T18

11

T80

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

323

1

T19

4

T18

4

T80

6

from_0to1

318

1

T19

4

T18

5

T80

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708

1

T19

12

T18

8

T80

7

auto[1]

654

1

T19

8

T18

12

T80

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692

1

T19

12

T18

10

T80

7

auto[1]

670

1

T19

8

T18

10

T80

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

30

1

T19

1

T18

1

T97

1

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T18

1

T97

1

T99

1

auto[0]

from_1to0

auto[1]

auto[0]

37

1

T80

1

T337

1

T333

1

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T19

1

T80

2

T181

1

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T18

1

T80

1

T97

2

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T19

1

T80

1

T86

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T19

1

T18

1

T80

1

auto[0]

from_0to1

auto[1]

auto[1]

30

1

T18

1

T97

1

T337

1

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T19

1

T18

1

T80

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T19

1

T97

2

T99

2

auto[1]

from_1to0

auto[1]

auto[0]

48

1

T80

1

T97

2

T337

1

auto[1]

from_1to0

auto[1]

auto[1]

35

1

T18

1

T80

1

T86

1

auto[1]

from_0to1

auto[0]

auto[0]

40

1

T19

1

T97

1

T99

2

auto[1]

from_0to1

auto[0]

auto[1]

36

1

T337

1

T294

1

T446

1

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T337

2

T181

1

T86

1

auto[1]

from_0to1

auto[1]

auto[1]

37

1

T19

1

T18

2

T80

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

734

1

T19

10

T18

11

T80

7

auto[1]

628

1

T19

10

T18

9

T80

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

328

1

T19

4

T18

5

T80

7

from_0to1

321

1

T19

3

T18

4

T80

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678

1

T19

13

T18

11

T80

12

auto[1]

684

1

T19

7

T18

9

T80

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

651

1

T19

8

T18

5

T80

10

auto[1]

711

1

T19

12

T18

15

T80

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T19

1

T99

1

T337

1

auto[0]

from_1to0

auto[0]

auto[1]

48

1

T19

1

T18

3

T80

2

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T18

1

T97

1

T99

2

auto[0]

from_1to0

auto[1]

auto[1]

48

1

T80

1

T97

1

T337

1

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T80

1

T337

1

T181

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T18

2

T99

2

T337

1

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T97

1

T86

1

T445

1

auto[0]

from_0to1

auto[1]

auto[1]

44

1

T19

1

T99

2

T181

1

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T80

2

T99

1

T445

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T18

1

T337

1

T181

2

auto[1]

from_1to0

auto[1]

auto[0]

33

1

T19

1

T80

1

T99

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T19

1

T80

1

T97

1

auto[1]

from_0to1

auto[0]

auto[0]

42

1

T18

1

T80

1

T97

2

auto[1]

from_0to1

auto[0]

auto[1]

39

1

T19

1

T80

2

T97

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T19

1

T80

1

T97

1

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T18

1

T80

1

T337

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

705

1

T19

11

T18

16

T80

11

auto[1]

657

1

T19

9

T18

4

T80

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

306

1

T19

3

T18

5

T80

5

from_0to1

310

1

T19

3

T18

6

T80

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

680

1

T19

12

T18

12

T80

14

auto[1]

682

1

T19

8

T18

8

T80

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

691

1

T19

12

T18

6

T80

13

auto[1]

671

1

T19

8

T18

14

T80

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T80

1

T97

1

T337

1

auto[0]

from_1to0

auto[0]

auto[1]

43

1

T18

2

T97

1

T99

2

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T19

2

T80

1

T99

1

auto[0]

from_1to0

auto[1]

auto[1]

42

1

T97

1

T99

1

T337

2

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T18

1

T80

1

T97

1

auto[0]

from_0to1

auto[0]

auto[1]

37

1

T18

2

T80

1

T99

1

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T19

1

T18

1

T80

2

auto[0]

from_0to1

auto[1]

auto[1]

35

1

T18

2

T333

1

T181

1

auto[1]

from_1to0

auto[0]

auto[0]

34

1

T19

1

T80

2

T97

1

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T18

2

T444

2

T127

1

auto[1]

from_1to0

auto[1]

auto[0]

30

1

T80

1

T181

2

T445

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T18

1

T445

1

T444

1

auto[1]

from_0to1

auto[0]

auto[0]

33

1

T19

1

T97

1

T99

1

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T19

1

T80

1

T99

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T337

1

T181

1

T445

1

auto[1]

from_0to1

auto[1]

auto[1]

30

1

T337

1

T181

1

T77

1