Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150770	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115122

1

T4

3

T5

1

T6

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141688	1			T4	3		T5	2		T6	27
values[0x0]	61746	1			T4	1		T5	1		T6	1
values[0x1]	62458	1			T4	2		T19	33		T20	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121639	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

144253

1

T4

3

T5

1

T6

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1027	1			T21	1		T60	1		T80	3
valid_sources[0x01]	892	1			T18	2		T170	3		T11	17
valid_sources[0x02]	1223	1			T79	1		T80	1		T99	1
valid_sources[0x03]	775	1			T64	1		T333	3		T177	3
valid_sources[0x04]	1165	1			T80	3		T87	2		T259	2
valid_sources[0x05]	975	1			T80	1		T64	1		T159	1
valid_sources[0x06]	950	1			T159	2		T47	1		T34	1
valid_sources[0x07]	903	1			T7	1		T30	1		T64	2
valid_sources[0x08]	869	1			T80	1		T64	1		T174	2
valid_sources[0x09]	836	1			T8	6		T95	1		T12	2
valid_sources[0x0a]	944	1			T20	1		T89	1		T64	3
valid_sources[0x0b]	1848	1			T7	1		T32	1		T168	19
valid_sources[0x0c]	1124	1			T80	1		T13	2		T64	2
valid_sources[0x0d]	1106	1			T80	1		T32	3		T99	1
valid_sources[0x0e]	1140	1			T16	1		T88	2		T159	3
valid_sources[0x0f]	1123	1			T16	1		T8	2		T30	2
valid_sources[0x10]	835	1			T18	2		T99	1		T113	3
valid_sources[0x11]	1049	1			T9	1		T447	11		T88	4
valid_sources[0x12]	1371	1			T99	1		T64	2		T444	1
valid_sources[0x13]	994	1			T2	1		T99	2		T89	1
valid_sources[0x14]	857	1			T7	1		T80	1		T64	2
valid_sources[0x15]	1196	1			T10	2		T32	3		T99	1
valid_sources[0x16]	1142	1			T338	1		T333	3		T181	2
valid_sources[0x17]	1134	1			T100	2		T64	4		T66	1
valid_sources[0x18]	1007	1			T30	3		T99	1		T66	1
valid_sources[0x19]	932	1			T16	4		T80	1		T95	1
valid_sources[0x1a]	1043	1			T61	1		T64	2		T66	1
valid_sources[0x1b]	1076	1			T21	3		T89	1		T64	3
valid_sources[0x1c]	1072	1			T79	1		T89	1		T64	2
valid_sources[0x1d]	1003	1			T32	1		T99	1		T64	2
valid_sources[0x1e]	1007	1			T87	1		T88	2		T159	2
valid_sources[0x1f]	1093	1			T18	6		T80	1		T64	1
valid_sources[0x20]	884	1			T80	3		T64	3		T333	1
valid_sources[0x21]	1106	1			T79	1		T87	1		T63	1
valid_sources[0x22]	908	1			T18	4		T64	1		T65	2
valid_sources[0x23]	778	1			T79	2		T80	1		T10	4
valid_sources[0x24]	1402	1			T18	3		T79	1		T83	1
valid_sources[0x25]	812	1			T99	2		T64	1		T333	8
valid_sources[0x26]	900	1			T16	1		T7	1		T79	1
valid_sources[0x27]	861	1			T7	1		T61	2		T87	2
valid_sources[0x28]	957	1			T6	2		T21	1		T18	2
valid_sources[0x29]	944	1			T6	1		T60	1		T30	2
valid_sources[0x2a]	975	1			T61	1		T80	1		T170	1
valid_sources[0x2b]	1371	1			T80	2		T99	1		T63	1
valid_sources[0x2c]	868	1			T7	2		T30	3		T444	3
valid_sources[0x2d]	946	1			T89	1		T64	2		T181	1
valid_sources[0x2e]	1017	1			T99	1		T64	2		T181	1
valid_sources[0x2f]	915	1			T79	1		T32	1		T100	8
valid_sources[0x30]	1110	1			T80	1		T32	1		T99	1
valid_sources[0x31]	844	1			T99	2		T113	20		T64	1
valid_sources[0x32]	1180	1			T80	1		T89	1		T34	2
valid_sources[0x33]	1022	1			T7	3		T28	44		T64	2
valid_sources[0x34]	932	1			T80	1		T99	4		T159	3
valid_sources[0x35]	1193	1			T99	1		T64	1		T159	1
valid_sources[0x36]	839	1			T7	1		T79	1		T80	2
valid_sources[0x37]	790	1			T6	1		T20	1		T79	1
valid_sources[0x38]	1035	1			T80	1		T99	2		T89	1
valid_sources[0x39]	854	1			T80	1		T100	1		T89	1
valid_sources[0x3a]	897	1			T79	1		T99	1		T338	2
valid_sources[0x3b]	1177	1			T18	1		T99	1		T63	1
valid_sources[0x3c]	739	1			T32	1		T99	1		T62	11
valid_sources[0x3d]	875	1			T80	1		T64	2		T177	5
valid_sources[0x3e]	973	1			T80	1		T99	1		T63	1
valid_sources[0x3f]	720	1			T17	1		T79	1		T80	1
valid_sources[0x40]	784	1			T6	1		T99	1		T64	3
valid_sources[0x41]	1094	1			T99	1		T64	2		T181	1
valid_sources[0x42]	1043	1			T80	1		T113	2		T267	1
valid_sources[0x43]	993	1			T6	1		T20	1		T16	1
valid_sources[0x44]	997	1			T448	1		T64	5		T159	4
valid_sources[0x45]	827	1			T6	1		T15	7		T10	4
valid_sources[0x46]	1064	1			T10	7		T113	4		T64	1
valid_sources[0x47]	912	1			T18	1		T79	1		T80	1
valid_sources[0x48]	1040	1			T7	1		T99	1		T113	20
valid_sources[0x49]	990	1			T18	2		T79	1		T87	2
valid_sources[0x4a]	886	1			T80	2		T64	1		T159	5
valid_sources[0x4b]	848	1			T18	7		T99	1		T113	3
valid_sources[0x4c]	882	1			T79	1		T100	1		T64	1
valid_sources[0x4d]	792	1			T79	1		T9	2		T64	2
valid_sources[0x4e]	841	1			T79	1		T32	1		T84	1
valid_sources[0x4f]	1133	1			T7	1		T80	1		T99	1
valid_sources[0x50]	1110	1			T7	1		T30	4		T64	2
valid_sources[0x51]	1179	1			T79	1		T87	1		T168	3
valid_sources[0x52]	923	1			T99	1		T259	1		T64	1
valid_sources[0x53]	1262	1			T14	2		T12	1		T64	1
valid_sources[0x54]	2201	1			T99	1		T260	1		T159	4
valid_sources[0x55]	843	1			T6	1		T79	3		T80	1
valid_sources[0x56]	945	1			T18	7		T30	2		T99	1
valid_sources[0x57]	1507	1			T18	3		T8	2		T89	2
valid_sources[0x58]	1785	1			T2	1		T18	3		T88	1
valid_sources[0x59]	1118	1			T30	1		T87	3		T259	2
valid_sources[0x5a]	957	1			T170	1		T447	4		T99	1
valid_sources[0x5b]	1237	1			T99	1		T64	1		T181	1
valid_sources[0x5c]	1235	1			T6	1		T87	2		T64	1
valid_sources[0x5d]	913	1			T16	1		T79	1		T95	1
valid_sources[0x5e]	1246	1			T12	1		T87	1		T32	1
valid_sources[0x5f]	1206	1			T80	1		T448	2		T338	1
valid_sources[0x60]	1410	1			T6	1		T80	1		T88	1
valid_sources[0x61]	1064	1			T8	2		T31	8		T87	1
valid_sources[0x62]	951	1			T80	1		T170	1		T32	1
valid_sources[0x63]	1098	1			T79	1		T80	1		T88	2
valid_sources[0x64]	885	1			T6	2		T87	1		T63	1
valid_sources[0x65]	705	1			T6	1		T79	2		T80	2
valid_sources[0x66]	886	1			T87	2		T64	3		T75	1
valid_sources[0x67]	826	1			T64	5		T333	7		T48	1
valid_sources[0x68]	876	1			T18	1		T80	1		T84	1
valid_sources[0x69]	969	1			T80	2		T64	3		T159	1
valid_sources[0x6a]	2043	1			T79	1		T9	1		T99	1
valid_sources[0x6b]	974	1			T80	3		T166	2		T88	1
valid_sources[0x6c]	967	1			T6	1		T18	5		T3	4
valid_sources[0x6d]	1163	1			T2	2		T89	4		T34	2
valid_sources[0x6e]	990	1			T60	2		T81	2		T9	1
valid_sources[0x6f]	892	1			T30	2		T80	2		T9	3
valid_sources[0x70]	961	1			T79	1		T80	1		T64	1
valid_sources[0x71]	1019	1			T6	1		T79	1		T80	1
valid_sources[0x72]	1022	1			T20	1		T79	1		T87	2
valid_sources[0x73]	860	1			T9	2		T259	2		T64	1
valid_sources[0x74]	1091	1			T18	4		T64	1		T333	1
valid_sources[0x75]	807	1			T18	6		T60	2		T80	1
valid_sources[0x76]	826	1			T81	2		T87	3		T99	1
valid_sources[0x77]	872	1			T15	2		T3	5		T80	2
valid_sources[0x78]	1023	1			T64	1		T333	12		T444	1
valid_sources[0x79]	1123	1			T80	1		T9	1		T99	2
valid_sources[0x7a]	1138	1			T79	1		T167	3		T100	1
valid_sources[0x7b]	920	1			T100	3		T338	1		T34	3
valid_sources[0x7c]	935	1			T80	1		T87	1		T64	1
valid_sources[0x7d]	876	1			T7	1		T83	1		T64	3
valid_sources[0x7e]	1174	1			T17	1		T79	1		T99	1
valid_sources[0x7f]	1003	1			T79	1		T80	1		T81	1
valid_sources[0x80]	884	1			T18	3		T61	1		T87	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62787

1

T4

2

T5

1

T6

11

values[0x0]

all_enables

biggest_size

30443

1

T6

1

T19

10

T21

2

values[0x1]

all_enables

biggest_size

21892

1

T4

1

T19

4

T21

1