Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1291985542 11220 0 0
auto_block_debounce_ctl_rd_A 1291985542 1927 0 0
auto_block_out_ctl_rd_A 1291985542 2331 0 0
com_det_ctl_0_rd_A 1291985542 3502 0 0
com_det_ctl_1_rd_A 1291985542 3777 0 0
com_det_ctl_2_rd_A 1291985542 3581 0 0
com_det_ctl_3_rd_A 1291985542 3524 0 0
com_out_ctl_0_rd_A 1291985542 3747 0 0
com_out_ctl_1_rd_A 1291985542 3723 0 0
com_out_ctl_2_rd_A 1291985542 3708 0 0
com_out_ctl_3_rd_A 1291985542 3757 0 0
com_pre_det_ctl_0_rd_A 1291985542 1672 0 0
com_pre_det_ctl_1_rd_A 1291985542 1726 0 0
com_pre_det_ctl_2_rd_A 1291985542 1809 0 0
com_pre_det_ctl_3_rd_A 1291985542 1775 0 0
com_pre_sel_ctl_0_rd_A 1291985542 3933 0 0
com_pre_sel_ctl_1_rd_A 1291985542 4009 0 0
com_pre_sel_ctl_2_rd_A 1291985542 3794 0 0
com_pre_sel_ctl_3_rd_A 1291985542 3711 0 0
com_sel_ctl_0_rd_A 1291985542 3999 0 0
com_sel_ctl_1_rd_A 1291985542 3855 0 0
com_sel_ctl_2_rd_A 1291985542 4029 0 0
com_sel_ctl_3_rd_A 1291985542 4224 0 0
ec_rst_ctl_rd_A 1291985542 2468 0 0
intr_enable_rd_A 1291985542 1987 0 0
key_intr_ctl_rd_A 1291985542 2661 0 0
key_intr_debounce_ctl_rd_A 1291985542 1846 0 0
key_invert_ctl_rd_A 1291985542 4018 0 0
pin_allowed_ctl_rd_A 1291985542 3928 0 0
pin_out_ctl_rd_A 1291985542 3530 0 0
pin_out_value_rd_A 1291985542 3227 0 0
regwen_rd_A 1291985542 1744 0 0
ulp_ac_debounce_ctl_rd_A 1291985542 2006 0 0
ulp_ctl_rd_A 1291985542 1962 0 0
ulp_lid_debounce_ctl_rd_A 1291985542 1876 0 0
ulp_pwrb_debounce_ctl_rd_A 1291985542 1896 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 11220 0 0
T13 334463 0 0 0
T63 112085 0 0 0
T64 435784 3 0 0
T65 0 2 0 0
T84 203120 0 0 0
T89 59361 0 0 0
T100 261210 0 0 0
T106 0 5 0 0
T107 0 17 0 0
T113 325003 11 0 0
T129 0 8 0 0
T159 0 7 0 0
T258 410457 0 0 0
T259 64102 0 0 0
T277 0 6 0 0
T278 0 7 0 0
T333 0 8 0 0
T334 200806 0 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1927 0 0
T3 119518 0 0 0
T7 62295 0 0 0
T8 114537 0 0 0
T16 72634 10 0 0
T17 48497 0 0 0
T18 60820 0 0 0
T27 121542 0 0 0
T30 141586 0 0 0
T60 103631 0 0 0
T61 48243 0 0 0
T65 0 18 0 0
T68 0 10 0 0
T69 0 4 0 0
T107 0 34 0 0
T129 0 14 0 0
T160 0 9 0 0
T270 0 17 0 0
T278 0 20 0 0
T335 0 16 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 2331 0 0
T3 119518 0 0 0
T7 62295 0 0 0
T8 114537 0 0 0
T16 72634 11 0 0
T17 48497 0 0 0
T18 60820 0 0 0
T27 121542 0 0 0
T30 141586 0 0 0
T60 103631 0 0 0
T61 48243 0 0 0
T65 0 8 0 0
T68 0 5 0 0
T69 0 7 0 0
T107 0 21 0 0
T129 0 6 0 0
T160 0 13 0 0
T270 0 8 0 0
T278 0 22 0 0
T335 0 19 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3502 0 0
T40 0 82 0 0
T58 0 59 0 0
T65 94378 8 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 15 0 0
T110 0 33 0 0
T118 0 44 0 0
T129 0 26 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 6 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 18 0 0
T336 0 10 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3777 0 0
T40 0 60 0 0
T58 0 84 0 0
T65 94378 11 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 20 0 0
T110 0 31 0 0
T118 0 63 0 0
T129 0 16 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 25 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 28 0 0
T336 0 18 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3581 0 0
T40 0 79 0 0
T58 0 64 0 0
T65 94378 21 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 26 0 0
T110 0 18 0 0
T118 0 53 0 0
T129 0 27 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 19 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 14 0 0
T336 0 15 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3524 0 0
T40 0 72 0 0
T58 0 66 0 0
T65 94378 9 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 12 0 0
T110 0 34 0 0
T118 0 45 0 0
T129 0 18 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 17 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 19 0 0
T336 0 21 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3747 0 0
T40 0 68 0 0
T58 0 63 0 0
T65 94378 5 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 13 0 0
T110 0 43 0 0
T118 0 65 0 0
T129 0 3 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 21 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 21 0 0
T336 0 20 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3723 0 0
T40 0 61 0 0
T58 0 58 0 0
T65 94378 12 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 24 0 0
T110 0 32 0 0
T118 0 49 0 0
T129 0 14 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 15 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 21 0 0
T336 0 26 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3708 0 0
T40 0 47 0 0
T58 0 66 0 0
T65 94378 24 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 22 0 0
T110 0 35 0 0
T118 0 48 0 0
T129 0 23 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 9 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 30 0 0
T336 0 21 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3757 0 0
T35 896553 0 0 0
T40 0 64 0 0
T58 0 85 0 0
T92 234349 0 0 0
T107 816898 22 0 0
T110 0 37 0 0
T118 0 69 0 0
T124 326063 0 0 0
T125 195012 0 0 0
T126 195219 0 0 0
T127 60867 0 0 0
T128 55244 0 0 0
T129 259258 15 0 0
T221 0 1 0 0
T243 740266 0 0 0
T278 0 13 0 0
T335 0 22 0 0
T336 0 3 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1672 0 0
T65 94378 14 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 8 0 0
T110 0 34 0 0
T129 0 14 0 0
T159 249721 0 0 0
T221 0 10 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 25 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 19 0 0
T336 0 16 0 0
T337 68279 0 0 0
T338 224532 0 0 0
T339 0 17 0 0
T340 0 26 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1726 0 0
T65 94378 16 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 14 0 0
T110 0 22 0 0
T159 249721 0 0 0
T221 0 22 0 0
T248 0 28 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 29 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 12 0 0
T336 0 14 0 0
T337 68279 0 0 0
T338 224532 0 0 0
T339 0 13 0 0
T340 0 39 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1809 0 0
T65 94378 18 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 15 0 0
T110 0 23 0 0
T129 0 9 0 0
T159 249721 0 0 0
T221 0 3 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 24 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 14 0 0
T336 0 21 0 0
T337 68279 0 0 0
T338 224532 0 0 0
T339 0 16 0 0
T340 0 20 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1775 0 0
T65 94378 8 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 19 0 0
T110 0 17 0 0
T129 0 2 0 0
T159 249721 0 0 0
T221 0 14 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 22 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 23 0 0
T336 0 17 0 0
T337 68279 0 0 0
T338 224532 0 0 0
T339 0 26 0 0
T340 0 37 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3933 0 0
T40 0 63 0 0
T58 0 82 0 0
T65 94378 13 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 30 0 0
T110 0 33 0 0
T118 0 49 0 0
T129 0 11 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 25 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 23 0 0
T336 0 21 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 4009 0 0
T40 0 73 0 0
T58 0 61 0 0
T65 94378 8 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 24 0 0
T110 0 29 0 0
T118 0 76 0 0
T129 0 3 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 25 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 25 0 0
T336 0 14 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3794 0 0
T40 0 74 0 0
T58 0 58 0 0
T65 94378 11 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 10 0 0
T110 0 32 0 0
T118 0 50 0 0
T129 0 11 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 17 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 10 0 0
T336 0 10 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3711 0 0
T40 0 65 0 0
T58 0 70 0 0
T65 94378 9 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 22 0 0
T110 0 45 0 0
T118 0 59 0 0
T129 0 18 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 11 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 21 0 0
T336 0 21 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3999 0 0
T40 0 67 0 0
T58 0 69 0 0
T65 94378 7 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 29 0 0
T110 0 39 0 0
T118 0 41 0 0
T129 0 6 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 23 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 19 0 0
T336 0 15 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3855 0 0
T40 0 69 0 0
T58 0 71 0 0
T65 94378 16 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 20 0 0
T110 0 32 0 0
T118 0 49 0 0
T129 0 11 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 30 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 10 0 0
T336 0 18 0 0
T337 68279 0 0 0
T338 224532 0 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 4029 0 0
T40 0 76 0 0
T58 0 68 0 0
T65 94378 5 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 16 0 0
T110 0 36 0 0
T118 0 42 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 20 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 25 0 0
T336 0 13 0 0
T337 68279 0 0 0
T338 224532 0 0 0
T339 0 17 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 4224 0 0
T40 0 76 0 0
T58 0 68 0 0
T65 94378 5 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 27 0 0
T110 0 35 0 0
T118 0 62 0 0
T129 0 16 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 22 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 16 0 0
T336 0 26 0 0
T337 68279 0 0 0
T338 224532 0 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 2468 0 0
T40 0 7 0 0
T65 94378 11 0 0
T69 0 2 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T102 0 1 0 0
T104 0 5 0 0
T107 0 16 0 0
T129 0 11 0 0
T159 249721 0 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T276 0 1 0 0
T278 0 34 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T337 68279 0 0 0
T338 224532 0 0 0
T341 0 2 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1987 0 0
T65 94378 23 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 48 0 0
T110 0 43 0 0
T129 0 8 0 0
T159 249721 0 0 0
T221 0 12 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 9 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 9 0 0
T336 0 15 0 0
T337 68279 0 0 0
T338 224532 0 0 0
T339 0 16 0 0
T340 0 16 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 2661 0 0
T48 0 2 0 0
T65 94378 4 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 17 0 0
T110 0 31 0 0
T129 0 9 0 0
T159 249721 0 0 0
T197 0 2 0 0
T221 0 3 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 15 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 6 0 0
T336 0 23 0 0
T337 68279 0 0 0
T338 224532 0 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1846 0 0
T65 94378 3 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 13 0 0
T110 0 35 0 0
T129 0 5 0 0
T159 249721 0 0 0
T221 0 9 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 22 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 20 0 0
T336 0 13 0 0
T337 68279 0 0 0
T338 224532 0 0 0
T339 0 23 0 0
T340 0 20 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 4018 0 0
T9 225448 0 0 0
T10 24449 0 0 0
T11 59456 0 0 0
T12 240384 0 0 0
T28 242197 48 0 0
T29 241065 0 0 0
T65 0 1 0 0
T77 0 67 0 0
T88 0 61 0 0
T90 0 57 0 0
T91 0 95 0 0
T93 0 26 0 0
T94 202626 0 0 0
T95 98047 0 0 0
T107 0 34 0 0
T129 0 5 0 0
T166 96937 0 0 0
T170 193256 0 0 0
T278 0 29 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3928 0 0
T3 119518 0 0 0
T7 62295 0 0 0
T8 114537 0 0 0
T18 60820 77 0 0
T27 121542 0 0 0
T30 141586 0 0 0
T60 103631 0 0 0
T61 48243 0 0 0
T65 0 5 0 0
T77 0 56 0 0
T78 463517 0 0 0
T79 31721 0 0 0
T80 0 51 0 0
T107 0 16 0 0
T129 0 16 0 0
T278 0 25 0 0
T294 0 64 0 0
T335 0 17 0 0
T342 0 40 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3530 0 0
T3 119518 0 0 0
T7 62295 0 0 0
T8 114537 0 0 0
T18 60820 69 0 0
T27 121542 0 0 0
T30 141586 0 0 0
T60 103631 0 0 0
T61 48243 0 0 0
T77 0 58 0 0
T78 463517 0 0 0
T79 31721 0 0 0
T80 0 54 0 0
T107 0 18 0 0
T129 0 5 0 0
T278 0 26 0 0
T294 0 59 0 0
T335 0 11 0 0
T336 0 28 0 0
T342 0 25 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 3227 0 0
T3 119518 0 0 0
T7 62295 0 0 0
T8 114537 0 0 0
T18 60820 54 0 0
T27 121542 0 0 0
T30 141586 0 0 0
T60 103631 0 0 0
T61 48243 0 0 0
T65 0 8 0 0
T77 0 71 0 0
T78 463517 0 0 0
T79 31721 0 0 0
T80 0 59 0 0
T107 0 33 0 0
T129 0 9 0 0
T278 0 15 0 0
T294 0 28 0 0
T335 0 9 0 0
T342 0 47 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1744 0 0
T65 94378 10 0 0
T90 116071 0 0 0
T101 227612 0 0 0
T107 0 44 0 0
T110 0 32 0 0
T129 0 9 0 0
T159 249721 0 0 0
T248 0 27 0 0
T261 23993 0 0 0
T262 42404 0 0 0
T278 0 25 0 0
T313 529643 0 0 0
T333 106011 0 0 0
T335 0 20 0 0
T336 0 21 0 0
T337 68279 0 0 0
T338 224532 0 0 0
T339 0 12 0 0
T340 0 19 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 2006 0 0
T8 114537 13 0 0
T10 0 10 0 0
T27 121542 0 0 0
T30 141586 0 0 0
T33 222078 0 0 0
T60 103631 0 0 0
T61 48243 0 0 0
T65 0 7 0 0
T69 0 1 0 0
T70 0 10 0 0
T76 0 11 0 0
T78 463517 0 0 0
T79 31721 0 0 0
T80 45874 0 0 0
T81 169900 0 0 0
T85 0 3 0 0
T107 0 26 0 0
T129 0 17 0 0
T278 0 16 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1962 0 0
T8 114537 10 0 0
T10 0 3 0 0
T27 121542 0 0 0
T30 141586 0 0 0
T33 222078 0 0 0
T60 103631 0 0 0
T61 48243 0 0 0
T69 0 6 0 0
T70 0 4 0 0
T76 0 13 0 0
T77 0 4 0 0
T78 463517 0 0 0
T79 31721 0 0 0
T80 45874 0 0 0
T81 169900 0 0 0
T85 0 2 0 0
T107 0 9 0 0
T129 0 6 0 0
T278 0 18 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1876 0 0
T8 114537 4 0 0
T10 0 13 0 0
T27 121542 0 0 0
T30 141586 0 0 0
T33 222078 0 0 0
T60 103631 0 0 0
T61 48243 0 0 0
T65 0 22 0 0
T70 0 6 0 0
T76 0 17 0 0
T78 463517 0 0 0
T79 31721 0 0 0
T80 45874 0 0 0
T81 169900 0 0 0
T85 0 7 0 0
T107 0 22 0 0
T108 0 5 0 0
T129 0 8 0 0
T278 0 20 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291985542 1896 0 0
T8 114537 11 0 0
T10 0 7 0 0
T27 121542 0 0 0
T30 141586 0 0 0
T33 222078 0 0 0
T60 103631 0 0 0
T61 48243 0 0 0
T65 0 7 0 0
T69 0 9 0 0
T76 0 8 0 0
T77 0 4 0 0
T78 463517 0 0 0
T79 31721 0 0 0
T80 45874 0 0 0
T81 169900 0 0 0
T85 0 2 0 0
T107 0 22 0 0
T129 0 7 0 0
T278 0 20 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%