dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_reg.u_intr_state

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.59 77.78 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_intr_enable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_regwen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ec_rst_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_ctl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_status

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_wkup_status

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_bat_disable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_ec_rst_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_pwrb_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_key0_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_key1_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_key2_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_z3_wakeup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_flash_wp_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_bat_disable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_ec_rst_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_pwrb_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_key0_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_key1_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_key2_out

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.59 77.78 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_pin_in_value_key0_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.59 77.78 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_pin_in_value_key1_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.59 77.78 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_pin_in_value_key2_in

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.59 77.78 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00


Module Instance : tb.dut.u_reg.u_pin_in_value_lid_open

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.59 77.78 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 50.00 50.00

Go back
Module Instances:
tb.dut.u_reg.u_intr_state
tb.dut.u_reg.u_intr_enable
tb.dut.u_reg.u_regwen
tb.dut.u_reg.u_ec_rst_ctl
tb.dut.u_reg.u_ulp_ac_debounce_ctl
tb.dut.u_reg.u_ulp_lid_debounce_ctl
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl
tb.dut.u_reg.u_ulp_ctl
tb.dut.u_reg.u_ulp_status
tb.dut.u_reg.u_wkup_status
tb.dut.u_reg.u_key_invert_ctl_key0_in
tb.dut.u_reg.u_key_invert_ctl_key0_out
tb.dut.u_reg.u_key_invert_ctl_key1_in
tb.dut.u_reg.u_key_invert_ctl_key1_out
tb.dut.u_reg.u_key_invert_ctl_key2_in
tb.dut.u_reg.u_key_invert_ctl_key2_out
tb.dut.u_reg.u_key_invert_ctl_pwrb_in
tb.dut.u_reg.u_key_invert_ctl_pwrb_out
tb.dut.u_reg.u_key_invert_ctl_ac_present
tb.dut.u_reg.u_key_invert_ctl_bat_disable
tb.dut.u_reg.u_key_invert_ctl_lid_open
tb.dut.u_reg.u_key_invert_ctl_z3_wakeup
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0
tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1
tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1
tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1
tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1
tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1
tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1
tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1
tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1
tb.dut.u_reg.u_pin_out_ctl_bat_disable
tb.dut.u_reg.u_pin_out_ctl_ec_rst_l
tb.dut.u_reg.u_pin_out_ctl_pwrb_out
tb.dut.u_reg.u_pin_out_ctl_key0_out
tb.dut.u_reg.u_pin_out_ctl_key1_out
tb.dut.u_reg.u_pin_out_ctl_key2_out
tb.dut.u_reg.u_pin_out_ctl_z3_wakeup
tb.dut.u_reg.u_pin_out_ctl_flash_wp_l
tb.dut.u_reg.u_pin_out_value_bat_disable
tb.dut.u_reg.u_pin_out_value_ec_rst_l
tb.dut.u_reg.u_pin_out_value_pwrb_out
tb.dut.u_reg.u_pin_out_value_key0_out
tb.dut.u_reg.u_pin_out_value_key1_out
tb.dut.u_reg.u_pin_out_value_key2_out
tb.dut.u_reg.u_pin_out_value_z3_wakeup
tb.dut.u_reg.u_pin_out_value_flash_wp_l
tb.dut.u_reg.u_pin_in_value_pwrb_in
tb.dut.u_reg.u_pin_in_value_key0_in
tb.dut.u_reg.u_pin_in_value_key1_in
tb.dut.u_reg.u_pin_in_value_key2_in
tb.dut.u_reg.u_pin_in_value_lid_open
Line Coverage for Instance : tb.dut.u_reg.u_intr_state
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T5 T6 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==> (Excluded)

Branches:
-1-StatusTestsExclude Annotation
1 Covered T4,T5,T6
0 Excluded VC_COV_UNR 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T5 T6 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         1/1            assign qe = wr_en;
           Tests:       T4 T5 T6 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_regwen
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T38 T22 T39 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         1/1            assign qe = wr_en;
           Tests:       T37 T38 T22 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_regwen
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT38,T22,T39
Branch Coverage for Instance : tb.dut.u_reg.u_regwen
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T38,T22,T39
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T38,T22,T39
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T2 T15 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T2 T15 
65         1/1            assign qe = wr_en;
           Tests:       T4 T2 T15 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T2 T15 
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T2,T15
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T4,T2,T15
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T2,T15
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T8 T9 T10 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T8 T9 T10 
65         1/1            assign qe = wr_en;
           Tests:       T8 T9 T10 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T8 T9 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT8,T9,T10
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T8,T9,T10
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T8 T9 T10 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T8 T9 T10 
65         1/1            assign qe = wr_en;
           Tests:       T8 T9 T10 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T8 T9 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT8,T9,T10
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T8,T9,T10
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T8 T9 T10 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T8 T9 T10 
65         1/1            assign qe = wr_en;
           Tests:       T8 T9 T10 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T8 T9 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT8,T9,T10
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T8,T9,T10
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T8 T9 T10 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T8 T9 T10 
65         1/1            assign qe = wr_en;
           Tests:       T8 T9 T10 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T8 T9 T10 
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT8,T9,T10
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T8,T9,T10
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T8 T9 T10 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         1/1            assign qe = wr_en;
           Tests:       T4 T5 T6 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT8,T9,T10
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T8,T9,T10
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T2 T3 
65         1/1            assign qe = wr_en;
           Tests:       T1 T2 T3 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T1,T2,T3
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T27 T28 T29 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T28 T29 
65         1/1            assign qe = wr_en;
           Tests:       T27 T28 T29 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T28 T29 
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT27,T28,T29
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T27,T28,T29
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key1_out_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key2_out_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_z3_wakeup_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_flash_wp_l_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_bat_disable
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T19 T2 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T19 T2 
65         1/1            assign qe = wr_en;
           Tests:       T4 T19 T2 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_bat_disable
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T19,T2
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_bat_disable
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T4,T19,T2
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T19,T2
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_ec_rst_l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T19 T2 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T19 T2 
65         1/1            assign qe = wr_en;
           Tests:       T4 T19 T2 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T19 T2 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_ec_rst_l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T19,T2
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_ec_rst_l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T4,T19,T2
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T19,T2
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_pwrb_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T19 T2 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T19 T2 
65         1/1            assign qe = wr_en;
           Tests:       T4 T19 T2 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_pwrb_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T19,T2
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_pwrb_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T4,T19,T2
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T19,T2
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key0_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T19 T2 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T19 T2 
65         1/1            assign qe = wr_en;
           Tests:       T4 T19 T2 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key0_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T19,T2
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key0_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T4,T19,T2
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T19,T2
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key1_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T19 T2 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T19 T2 
65         1/1            assign qe = wr_en;
           Tests:       T4 T19 T2 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key1_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T19,T2
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key1_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T4,T19,T2
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T19,T2
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key2_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T19 T2 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T19 T2 
65         1/1            assign qe = wr_en;
           Tests:       T4 T19 T2 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key2_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T19,T2
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_key2_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T4,T19,T2
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T19,T2
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_z3_wakeup
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T19 T2 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T19 T2 
65         1/1            assign qe = wr_en;
           Tests:       T4 T19 T2 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_z3_wakeup
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T19,T2
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_z3_wakeup
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T4,T19,T2
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T19,T2
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_flash_wp_l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T19 T2 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T19 T2 
65         1/1            assign qe = wr_en;
           Tests:       T4 T19 T2 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_flash_wp_l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T19,T2
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_flash_wp_l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T4,T19,T2
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T19,T2
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_bat_disable
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_bat_disable
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_bat_disable
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_ec_rst_l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_ec_rst_l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_ec_rst_l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_pwrb_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_pwrb_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_pwrb_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key0_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key0_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key0_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key1_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key1_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key1_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key2_out
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key2_out
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_key2_out
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_z3_wakeup
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T19 T18 T30 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T19 T18 T30 
65         1/1            assign qe = wr_en;
           Tests:       T19 T18 T30 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T19 T18 T30 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT19,T18,T30
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_flash_wp_l
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T19,T18,T30
0 Covered T4,T5,T6 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T19,T18,T30
0 0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T5 T6 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_pwrb_in
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==> (Excluded)

Branches:
-1-StatusTestsExclude Annotation
1 Covered T4,T5,T6
0 Excluded VC_COV_UNR 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key0_in
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T5 T6 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key0_in
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key0_in
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==> (Excluded)

Branches:
-1-StatusTestsExclude Annotation
1 Covered T4,T5,T6
0 Excluded VC_COV_UNR 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key1_in
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T5 T6 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key1_in
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key1_in
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==> (Excluded)

Branches:
-1-StatusTestsExclude Annotation
1 Covered T4,T5,T6
0 Excluded VC_COV_UNR 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key2_in
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T5 T6 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key2_in
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_key2_in
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==> (Excluded)

Branches:
-1-StatusTestsExclude Annotation
1 Covered T4,T5,T6
0 Excluded VC_COV_UNR 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_reg.u_pin_in_value_lid_open
Line No.TotalCoveredPercent
TOTAL7685.71
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN65100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
57         1/1                q <= RESVAL;
           Tests:       T4 T5 T6 
58         1/1              end else if (wr_en) begin
           Tests:       T4 T5 T6 
59         1/1                q <= wr_data;
           Tests:       T4 T5 T6 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T4 T5 T6 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T4 T5 T6 
Cond Coverage for Instance : tb.dut.u_reg.u_pin_in_value_lid_open
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_reg.u_pin_in_value_lid_open
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 64 1 1 100.00
IF 56 2 2 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==> (Excluded)

Branches:
-1-StatusTestsExclude Annotation
1 Covered T4,T5,T6
0 Excluded VC_COV_UNR 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Excluded VC_COV_UNR

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%