Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg
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Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_key_intr_status_cg 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_key_intr_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_key_intr_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_key_intr_status_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_h2l 2 0 2 100.00 100 1 1 2
cp_ac_present_l2h 2 0 2 100.00 100 1 1 2
cp_ec_rst_l_h2l 2 0 2 100.00 100 1 1 2
cp_ec_rst_l_l2h 2 0 2 100.00 100 1 1 2
cp_flash_wp_l_h2l 2 0 2 100.00 100 1 1 2
cp_flash_wp_l_l2h 2 0 2 100.00 100 1 1 2
cp_key0_in_h2l 2 0 2 100.00 100 1 1 2
cp_key0_in_l2h 2 0 2 100.00 100 1 1 2
cp_key1_in_h2l 2 0 2 100.00 100 1 1 2
cp_key1_in_l2h 2 0 2 100.00 100 1 1 2
cp_key2_in_h2l 2 0 2 100.00 100 1 1 2
cp_key2_in_l2h 2 0 2 100.00 100 1 1 2
cp_pwrb_h2l 2 0 2 100.00 100 1 1 2
cp_pwrb_l2h 2 0 2 100.00 100 1 1 2


Summary for Variable cp_ac_present_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_h2l

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1045 1 T23 8 T2 7 T7 5
auto[1] 62 1 T13 3 T94 1 T34 1



Summary for Variable cp_ac_present_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_l2h

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1033 1 T23 8 T2 5 T7 5
auto[1] 74 1 T2 2 T8 3 T34 1



Summary for Variable cp_ec_rst_l_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l_h2l

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1021 1 T23 8 T2 7 T7 5
auto[1] 86 1 T8 4 T13 4 T34 1



Summary for Variable cp_ec_rst_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l_l2h

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1058 1 T23 8 T2 7 T7 5
auto[1] 49 1 T8 2 T13 3 T34 1



Summary for Variable cp_flash_wp_l_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l_h2l

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1016 1 T23 8 T2 7 T7 3
auto[1] 91 1 T7 2 T8 2 T34 1



Summary for Variable cp_flash_wp_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l_l2h

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1050 1 T23 8 T2 3 T7 5
auto[1] 57 1 T2 4 T8 1 T94 1



Summary for Variable cp_key0_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_h2l

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1035 1 T23 8 T2 4 T7 3
auto[1] 72 1 T2 3 T7 2 T52 2



Summary for Variable cp_key0_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_l2h

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1035 1 T23 8 T2 7 T7 3
auto[1] 72 1 T7 2 T8 3 T34 1



Summary for Variable cp_key1_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_h2l

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1046 1 T23 8 T2 5 T7 3
auto[1] 61 1 T2 2 T7 2 T8 1



Summary for Variable cp_key1_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_l2h

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1014 1 T23 8 T2 4 T7 5
auto[1] 93 1 T2 3 T13 2 T52 2



Summary for Variable cp_key2_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_h2l

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1055 1 T23 8 T2 5 T7 2
auto[1] 52 1 T2 2 T7 3 T34 1



Summary for Variable cp_key2_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_l2h

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1039 1 T23 8 T2 7 T7 5
auto[1] 68 1 T13 3 T34 1 T36 1



Summary for Variable cp_pwrb_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_h2l

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1050 1 T23 8 T2 4 T7 5
auto[1] 57 1 T2 3 T94 1 T34 1



Summary for Variable cp_pwrb_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_l2h

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1029 1 T23 8 T2 7 T7 2
auto[1] 78 1 T7 3 T34 1 T36 1