Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1884

1

T35

32

T46

11

T59

32

auto[1]

513

1

T59

8

T49

1

T57

8

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1831

1

T35

24

T59

40

T57

2

auto[1]

566

1

T35

8

T46

11

T49

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1825

1

T35

32

T46

11

T59

32

auto[1]

572

1

T59

8

T49

2

T57

4

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1847

1

T35

32

T46

9

T59

28

auto[1]

550

1

T46

2

T59

12

T57

7

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2117

1

T35

24

T46

11

T59

36

auto[1]

280

1

T35

8

T59

4

T58

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2195

1

T35

32

T46

11

T59

24

auto[1]

202

1

T59

16

T48

4

T97

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2209

1

T35

24

T46

11

T59

40

auto[1]

188

1

T35

8

T48

7

T43

13

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2245

1

T35

32

T46

11

T59

40

auto[1]

152

1

T58

3

T48

2

T45

11

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2205

1

T35

32

T46

11

T59

40

auto[1]

192

1

T48

2

T97

7

T43

13

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1821

1

T35

32

T46

9

T59

32

auto[1]

576

1

T46

2

T59

8

T57

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

808

1

T46

11

T49

2

T57

10

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

92

1

T59

3

T228

3

T127

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T97

7

T43

5

T229

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

47

1

T45

2

T373

3

T248

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

35

1

T45

6

T373

4

T374

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T58

3

T375

6

T113

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T48

2

T45

5

T373

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

34

1

T43

5

T45

6

T122

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T35

8

T48

3

T376

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

17

1

T43

4

T377

2

T378

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T229

2

T360

7

T213

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

8

1

T379

1

T380

2

T381

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T360

5

T249

1

T382

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T376

3

T359

2

T383

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

42

1

T59

2

T97

2

T228

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T384

3

T385

3

T386

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

15

1

T387

1

T374

3

T369

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T354

4

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

24

1

T375

8

T369

5

T388

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T367

4

T372

4

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1

1

T228

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

26

1

T48

4

T122

1

T232

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T389

4

T390

2

T372

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

5

1

T43

4

T391

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

86

1

T59

1

T48

5

T120

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

140

1

T47

3

T44

9

T122

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T45

6

T252

6

T392

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

102

1

T59

3

T97

7

T43

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

52

1

T169

5

T350

5

T377

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

57

1

T48

3

T349

6

T125

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

31

1

T44

4

T245

2

T169

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

97

1

T48

1

T373

3

T348

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

58

1

T118

2

T44

7

T45

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T233

5

T347

4

T346

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T126

2

T393

4

T394

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T47

4

T228

3

T229

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T57

2

T124

4

T365

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T59

1

T97

2

T253

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T234

4

T126

1

T366

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

116

1

T35

8

T46

9

T350

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

41

1

T57

6

T366

8

T376

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T58

3

T44

6

T233

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T43

5

T233

1

T347

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

35

1

T45

2

T229

2

T353

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T43

4

T245

4

T121

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

16

1

T46

2

T233

2

T228

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T245

1

T346

6

T368

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

87

1

T49

1

T118

5

T169

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T49

1

T103

1

T43

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

32

1

T121

2

T351

1

T237

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T221

3

T252

4

T255

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

17

1

T57

2

T365

2

T236

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T349

1

T357

1

T352

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T351

1

T247

1

T355

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T392

1

T255

1

T368

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded