Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_key_invert_ctl_cg	100.00	1	100	1	64	64
sysrst_ctrl_key_invert_ctl_cg_(1)	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_key_invert_ctl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_invert_ctl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	48	0	48	100.00
Crosses	44	0	44	100.00

Variables for Group Instance sysrst_ctrl_key_invert_ctl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cfg.vif.ac_present	2	0	2	100.00	100	1	1	2
cfg.vif.bat_disable	2	0	2	100.00	100	1	1	2
cfg.vif.key0_in	2	0	2	100.00	100	1	1	2
cfg.vif.key0_out	2	0	2	100.00	100	1	1	2
cfg.vif.key1_in	2	0	2	100.00	100	1	1	2
cfg.vif.key1_out	2	0	2	100.00	100	1	1	2
cfg.vif.key2_in	2	0	2	100.00	100	1	1	2
cfg.vif.key2_out	2	0	2	100.00	100	1	1	2
cfg.vif.lid_open	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_in	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_out	2	0	2	100.00	100	1	1	2
cfg.vif.z3_wakeup	2	0	2	100.00	100	1	1	2
cp_ac_present	2	0	2	100.00	100	1	1	2
cp_bat_disable	2	0	2	100.00	100	1	1	2
cp_key0_in	2	0	2	100.00	100	1	1	2
cp_key0_out	2	0	2	100.00	100	1	1	2
cp_key1_in	2	0	2	100.00	100	1	1	2
cp_key1_out	2	0	2	100.00	100	1	1	2
cp_key2_in	2	0	2	100.00	100	1	1	2
cp_key2_out	2	0	2	100.00	100	1	1	2
cp_lid_open	2	0	2	100.00	100	1	1	2
cp_pwrb_in	2	0	2	100.00	100	1	1	2
cp_pwrb_out	2	0	2	100.00	100	1	1	2
cp_z3_wakeup	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_key_invert_ctl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key0_inXval	4	0	4	100.00	100	1	1	0
key0_outXval	4	0	4	100.00	100	1	1	0
key1_inXval	4	0	4	100.00	100	1	1	0
key1_outXval	4	0	4	100.00	100	1	1	0
key2_inXval	4	0	4	100.00	100	1	1	0
key2_outXval	4	0	4	100.00	100	1	1	0
pwrb_inXval	4	0	4	100.00	100	1	1	0
pwrb_outXval	4	0	4	100.00	100	1	1	0
ac_presentXval	4	0	4	100.00	100	1	1	0
bat_disableXval	2	0	2	100.00	100	1	1	0
lid_openXval	4	0	4	100.00	100	1	1	0
z3_wakeupXval	2	0	2	100.00	100	1	1	0

---

Group Instance : sysrst_ctrl_key_invert_ctl_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	48	0	48	100.00
Crosses	44	0	44	100.00

Variables for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cfg.vif.ac_present	2	0	2	100.00	100	1	1	2
cfg.vif.bat_disable	2	0	2	100.00	100	1	1	2
cfg.vif.key0_in	2	0	2	100.00	100	1	1	2
cfg.vif.key0_out	2	0	2	100.00	100	1	1	2
cfg.vif.key1_in	2	0	2	100.00	100	1	1	2
cfg.vif.key1_out	2	0	2	100.00	100	1	1	2
cfg.vif.key2_in	2	0	2	100.00	100	1	1	2
cfg.vif.key2_out	2	0	2	100.00	100	1	1	2
cfg.vif.lid_open	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_in	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_out	2	0	2	100.00	100	1	1	2
cfg.vif.z3_wakeup	2	0	2	100.00	100	1	1	2
cp_ac_present	2	0	2	100.00	100	1	1	2
cp_bat_disable	2	0	2	100.00	100	1	1	2
cp_key0_in	2	0	2	100.00	100	1	1	2
cp_key0_out	2	0	2	100.00	100	1	1	2
cp_key1_in	2	0	2	100.00	100	1	1	2
cp_key1_out	2	0	2	100.00	100	1	1	2
cp_key2_in	2	0	2	100.00	100	1	1	2
cp_key2_out	2	0	2	100.00	100	1	1	2
cp_lid_open	2	0	2	100.00	100	1	1	2
cp_pwrb_in	2	0	2	100.00	100	1	1	2
cp_pwrb_out	2	0	2	100.00	100	1	1	2
cp_z3_wakeup	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key0_inXval	4	0	4	100.00	100	1	1	0
key0_outXval	4	0	4	100.00	100	1	1	0
key1_inXval	4	0	4	100.00	100	1	1	0
key1_outXval	4	0	4	100.00	100	1	1	0
key2_inXval	4	0	4	100.00	100	1	1	0
key2_outXval	4	0	4	100.00	100	1	1	0
pwrb_inXval	4	0	4	100.00	100	1	1	0
pwrb_outXval	4	0	4	100.00	100	1	1	0
ac_presentXval	4	0	4	100.00	100	1	1	0
bat_disableXval	2	0	2	100.00	100	1	1	0
lid_openXval	4	0	4	100.00	100	1	1	0
z3_wakeupXval	2	0	2	100.00	100	1	1	0

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

637

1

T4

11

T29

10

T30

8

auto[1]

603

1

T4

9

T29

10

T30

12

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

598

1

T4

11

T29

11

T30

11

auto[1]

642

1

T4

9

T29

9

T30

9

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

612

1

T4

10

T29

9

T30

10

auto[1]

628

1

T4

10

T29

11

T30

10

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

624

1

T4

10

T29

10

T30

8

auto[1]

616

1

T4

10

T29

10

T30

12

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

621

1

T4

10

T29

9

T30

5

auto[1]

619

1

T4

10

T29

11

T30

15

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620

1

T4

8

T29

14

T30

14

auto[1]

620

1

T4

12

T29

6

T30

6

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

626

1

T4

11

T29

11

T30

11

auto[1]

614

1

T4

9

T29

9

T30

9

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

627

1

T4

13

T29

8

T30

8

auto[1]

613

1

T4

7

T29

12

T30

12

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

590

1

T4

10

T29

8

T30

10

auto[1]

650

1

T4

10

T29

12

T30

10

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623

1

T4

6

T29

15

T30

11

auto[1]

617

1

T4

14

T29

5

T30

9

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

594

1

T4

10

T29

12

T30

11

auto[1]

646

1

T4

10

T29

8

T30

9

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

610

1

T4

8

T29

7

T30

10

auto[1]

630

1

T4

12

T29

13

T30

10

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

624

1

T4

9

T29

11

T30

11

auto[1]

616

1

T4

11

T29

9

T30

9

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

598

1

T4

11

T29

11

T30

11

auto[1]

642

1

T4

9

T29

9

T30

9

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619

1

T4

13

T29

10

T30

8

auto[1]

621

1

T4

7

T29

10

T30

12

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

615

1

T4

7

T29

7

T30

14

auto[1]

625

1

T4

13

T29

13

T30

6

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619

1

T4

12

T29

9

T30

9

auto[1]

621

1

T4

8

T29

11

T30

11

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

626

1

T4

14

T29

14

T30

12

auto[1]

614

1

T4

6

T29

6

T30

8

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645

1

T4

10

T29

8

T30

11

auto[1]

595

1

T4

10

T29

12

T30

9

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

606

1

T4

14

T29

11

T30

10

auto[1]

634

1

T4

6

T29

9

T30

10

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

641

1

T4

12

T29

16

T30

9

auto[1]

599

1

T4

8

T29

4

T30

11

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

635

1

T4

7

T29

9

T30

13

auto[1]

605

1

T4

13

T29

11

T30

7

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

640

1

T4

9

T29

10

T30

11

auto[1]

600

1

T4

11

T29

10

T30

9

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

610

1

T4

8

T29

7

T30

10

auto[1]

630

1

T4

12

T29

13

T30

10

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in

cfg.vif.key0_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

305

1

T4

6

T29

4

T30

5

auto[0]

auto[1]

314

1

T4

7

T29

6

T30

3

auto[1]

auto[0]

307

1

T4

4

T29

5

T30

5

auto[1]

auto[1]

314

1

T4

3

T29

5

T30

7

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out

cfg.vif.key0_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

309

1

T4

3

T29

3

T30

7

auto[0]

auto[1]

306

1

T4

4

T29

4

T30

7

auto[1]

auto[0]

315

1

T4

7

T29

7

T30

1

auto[1]

auto[1]

310

1

T4

6

T29

6

T30

5

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in

cfg.vif.key1_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

317

1

T4

6

T29

5

T30

4

auto[0]

auto[1]

302

1

T4

6

T29

4

T30

5

auto[1]

auto[0]

304

1

T4

4

T29

4

T30

1

auto[1]

auto[1]

317

1

T4

4

T29

7

T30

10

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out

cfg.vif.key1_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

320

1

T4

6

T29

10

T30

10

auto[0]

auto[1]

306

1

T4

8

T29

4

T30

2

auto[1]

auto[0]

300

1

T4

2

T29

4

T30

4

auto[1]

auto[1]

314

1

T4

4

T29

2

T30

4

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in

cfg.vif.key2_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

330

1

T4

6

T29

1

T30

6

auto[0]

auto[1]

315

1

T4

4

T29

7

T30

5

auto[1]

auto[0]

296

1

T4

5

T29

10

T30

5

auto[1]

auto[1]

299

1

T4

5

T29

2

T30

4

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out

cfg.vif.key2_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

311

1

T4

9

T29

1

T30

4

auto[0]

auto[1]

295

1

T4

5

T29

10

T30

6

auto[1]

auto[0]

316

1

T4

4

T29

7

T30

4

auto[1]

auto[1]

318

1

T4

2

T29

2

T30

6

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in

cfg.vif.pwrb_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

325

1

T4

3

T29

6

T30

7

auto[0]

auto[1]

310

1

T4

4

T29

3

T30

6

auto[1]

auto[0]

298

1

T4

3

T29

9

T30

4

auto[1]

auto[1]

307

1

T4

10

T29

2

T30

3

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out

cfg.vif.pwrb_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

313

1

T4

6

T29

5

T30

6

auto[0]

auto[1]

327

1

T4

3

T29

5

T30

5

auto[1]

auto[0]

281

1

T4

4

T29

7

T30

5

auto[1]

auto[1]

319

1

T4

7

T29

3

T30

4

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present

cfg.vif.ac_present

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

307

1

T4

4

T29

6

T30

5

auto[0]

auto[1]

317

1

T4

5

T29

5

T30

6

auto[1]

auto[0]

330

1

T4

7

T29

4

T30

3

auto[1]

auto[1]

286

1

T4

4

T29

5

T30

6

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable

cfg.vif.bat_disable

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

598

1

T4

11

T29

11

T30

11

auto[1]

auto[1]

642

1

T4

9

T29

9

T30

9

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open

cfg.vif.lid_open

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

307

1

T4

7

T29

6

T30

2

auto[0]

auto[1]

334

1

T4

5

T29

10

T30

7

auto[1]

auto[0]

283

1

T4

3

T29

2

T30

8

auto[1]

auto[1]

316

1

T4

5

T29

2

T30

3

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup

cfg.vif.z3_wakeup

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

610

1

T4

8

T29

7

T30

10

auto[1]

auto[1]

630

1

T4

12

T29

13

T30

10

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	12	1			T417	12
auto[1]	8	1			T417	8

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	13	1			T417	13
auto[1]	7	1			T417	7

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	11	1			T417	11
auto[1]	9	1			T417	9

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	6	1			T417	6
auto[1]	14	1			T417	14

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	10	1			T417	10
auto[1]	10	1			T417	10

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	6	1			T417	6
auto[1]	14	1			T417	14

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	13	1			T417	13
auto[1]	7	1			T417	7

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	9	1			T417	9
auto[1]	11	1			T417	11

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	10	1			T417	10
auto[1]	10	1			T417	10

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	9	1			T417	9
auto[1]	11	1			T417	11

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	11	1			T417	11
auto[1]	9	1			T417	9

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	11	1			T417	11
auto[1]	9	1			T417	9

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	9	1			T417	9
auto[1]	11	1			T417	11

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	13	1			T417	13
auto[1]	7	1			T417	7

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	11	1			T417	11
auto[1]	9	1			T417	9

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	10	1			T417	10
auto[1]	10	1			T417	10

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	8	1			T417	8
auto[1]	12	1			T417	12

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	8	1			T417	8
auto[1]	12	1			T417	12

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	9	1			T417	9
auto[1]	11	1			T417	11

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	9	1			T417	9
auto[1]	11	1			T417	11

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	8	1			T417	8
auto[1]	12	1			T417	12

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	10	1			T417	10
auto[1]	10	1			T417	10

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	8	1			T417	8
auto[1]	12	1			T417	12

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	11	1			T417	11
auto[1]	9	1			T417	9

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in	cfg.vif.key0_in	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	8	1			T417	8
auto[0]	auto[1]	3	1			T417	3
auto[1]	auto[0]	3	1			T417	3
auto[1]	auto[1]	6	1			T417	6

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out	cfg.vif.key0_out	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	5	1			T417	5
auto[0]	auto[1]	5	1			T417	5
auto[1]	auto[0]	1	1			T417	1
auto[1]	auto[1]	9	1			T417	9

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in	cfg.vif.key1_in	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	4	1			T417	4
auto[0]	auto[1]	4	1			T417	4
auto[1]	auto[0]	6	1			T417	6
auto[1]	auto[1]	6	1			T417	6

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out	cfg.vif.key1_out	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	2	1			T417	2
auto[0]	auto[1]	6	1			T417	6
auto[1]	auto[0]	4	1			T417	4
auto[1]	auto[1]	8	1			T417	8

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in	cfg.vif.key2_in	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	8	1			T417	8
auto[0]	auto[1]	1	1			T417	1
auto[1]	auto[0]	5	1			T417	5
auto[1]	auto[1]	6	1			T417	6

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out	cfg.vif.key2_out	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	6	1			T417	6
auto[0]	auto[1]	3	1			T417	3
auto[1]	auto[0]	3	1			T417	3
auto[1]	auto[1]	8	1			T417	8

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in	cfg.vif.pwrb_in	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	3	1			T417	3
auto[0]	auto[1]	7	1			T417	7
auto[1]	auto[0]	6	1			T417	6
auto[1]	auto[1]	4	1			T417	4

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out	cfg.vif.pwrb_out	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	3	1			T417	3
auto[0]	auto[1]	5	1			T417	5
auto[1]	auto[0]	8	1			T417	8
auto[1]	auto[1]	4	1			T417	4

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present	cfg.vif.ac_present	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	6	1			T417	6
auto[0]	auto[1]	3	1			T417	3
auto[1]	auto[0]	6	1			T417	6
auto[1]	auto[1]	5	1			T417	5

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable	cfg.vif.bat_disable	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	13	1			T417	13
auto[1]	auto[1]	7	1			T417	7

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open	cfg.vif.lid_open	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	2	1			T417	2
auto[0]	auto[1]	6	1			T417	6
auto[1]	auto[0]	8	1			T417	8
auto[1]	auto[1]	4	1			T417	4

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup	cfg.vif.z3_wakeup	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	11	1			T417	11
auto[1]	auto[1]	9	1			T417	9

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded