Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645

1

T16

14

T69

7

T83

10

auto[1]

668

1

T16

6

T69

13

T83

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

321

1

T16

6

T69

4

T83

4

from_0to1

322

1

T16

6

T69

4

T83

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

610

1

T16

11

T69

10

T83

10

auto[1]

703

1

T16

9

T69

10

T83

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

641

1

T16

10

T69

13

T83

10

auto[1]

672

1

T16

10

T69

7

T83

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

33

1

T16

2

T83

1

T327

1

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T83

2

T145

3

T327

2

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T16

1

T100

1

T101

2

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T69

1

T162

1

T100

1

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T16

1

T83

1

T100

1

auto[0]

from_0to1

auto[0]

auto[1]

33

1

T16

2

T69

1

T132

1

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T16

1

T100

1

T101

2

auto[0]

from_0to1

auto[1]

auto[1]

44

1

T16

1

T83

1

T162

1

auto[1]

from_1to0

auto[0]

auto[0]

34

1

T16

1

T92

1

T101

3

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T16

2

T162

2

T100

1

auto[1]

from_1to0

auto[1]

auto[0]

41

1

T69

1

T92

2

T100

2

auto[1]

from_1to0

auto[1]

auto[1]

41

1

T69

2

T83

1

T162

1

auto[1]

from_0to1

auto[0]

auto[0]

42

1

T69

2

T83

2

T92

1

auto[1]

from_0to1

auto[0]

auto[1]

32

1

T16

1

T101

1

T145

1

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T92

3

T162

1

T101

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T69

1

T83

1

T162

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

654

1

T16

9

T69

13

T83

14

auto[1]

659

1

T16

11

T69

7

T83

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

312

1

T16

6

T69

6

T83

5

from_0to1

320

1

T16

6

T69

7

T83

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

658

1

T16

9

T69

13

T83

12

auto[1]

655

1

T16

11

T69

7

T83

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T16

11

T69

10

T83

12

auto[1]

665

1

T16

9

T69

10

T83

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

31

1

T83

2

T92

1

T100

2

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T16

1

T69

4

T83

1

auto[0]

from_1to0

auto[1]

auto[0]

32

1

T101

2

T145

3

T321

1

auto[0]

from_1to0

auto[1]

auto[1]

36

1

T100

1

T145

1

T321

1

auto[0]

from_0to1

auto[0]

auto[0]

45

1

T69

3

T83

1

T100

1

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T16

1

T69

1

T83

1

auto[0]

from_0to1

auto[1]

auto[0]

35

1

T16

2

T69

1

T162

1

auto[0]

from_0to1

auto[1]

auto[1]

37

1

T16

1

T83

1

T92

2

auto[1]

from_1to0

auto[0]

auto[0]

34

1

T16

1

T83

1

T92

1

auto[1]

from_1to0

auto[0]

auto[1]

37

1

T16

1

T92

1

T162

1

auto[1]

from_1to0

auto[1]

auto[0]

48

1

T16

1

T69

1

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T16

2

T69

1

T162

2

auto[1]

from_0to1

auto[0]

auto[0]

40

1

T16

1

T92

1

T162

1

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T16

1

T162

1

T327

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T162

1

T100

2

T145

1

auto[1]

from_0to1

auto[1]

auto[1]

39

1

T69

2

T83

1

T92

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

660

1

T16

8

T69

10

T83

7

auto[1]

653

1

T16

12

T69

10

T83

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

305

1

T16

5

T69

5

T83

4

from_0to1

305

1

T16

6

T69

6

T83

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

656

1

T16

12

T69

13

T83

8

auto[1]

657

1

T16

8

T69

7

T83

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

644

1

T16

9

T69

7

T83

12

auto[1]

669

1

T16

11

T69

13

T83

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T162

1

T145

2

T133

2

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T16

2

T69

1

T92

2

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T101

2

T145

1

T327

1

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T16

1

T69

1

T83

2

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T69

1

T83

1

T162

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T16

2

T162

1

T145

1

auto[0]

from_0to1

auto[1]

auto[0]

29

1

T92

1

T101

1

T145

2

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T69

3

T83

1

T162

1

auto[1]

from_1to0

auto[0]

auto[0]

42

1

T16

2

T69

1

T83

1

auto[1]

from_1to0

auto[0]

auto[1]

34

1

T92

1

T162

2

T100

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T83

1

T100

1

T145

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T69

2

T162

2

T100

1

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T69

2

T92

1

T100

1

auto[1]

from_0to1

auto[0]

auto[1]

34

1

T16

3

T83

1

T100

1

auto[1]

from_0to1

auto[1]

auto[0]

31

1

T16

1

T162

2

T101

1

auto[1]

from_0to1

auto[1]

auto[1]

44

1

T83

2

T92

1

T101

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

649

1

T16

13

T69

9

T83

12

auto[1]

664

1

T16

7

T69

11

T83

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

311

1

T16

7

T69

4

T83

5

from_0to1

307

1

T16

7

T69

5

T83

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

655

1

T16

11

T69

10

T83

12

auto[1]

658

1

T16

9

T69

10

T83

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

653

1

T16

6

T69

12

T83

10

auto[1]

660

1

T16

14

T69

8

T83

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T69

1

T83

2

T92

1

auto[0]

from_1to0

auto[0]

auto[1]

44

1

T16

1

T83

1

T145

1

auto[0]

from_1to0

auto[1]

auto[0]

38

1

T83

1

T92

3

T162

3

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T16

3

T92

1

T100

1

auto[0]

from_0to1

auto[0]

auto[0]

31

1

T16

1

T69

1

T92

1

auto[0]

from_0to1

auto[0]

auto[1]

33

1

T16

2

T83

1

T162

1

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T16

1

T69

1

T92

1

auto[0]

from_0to1

auto[1]

auto[1]

39

1

T83

1

T92

1

T101

1

auto[1]

from_1to0

auto[0]

auto[0]

30

1

T16

1

T100

1

T321

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T16

1

T69

1

T162

2

auto[1]

from_1to0

auto[1]

auto[0]

41

1

T83

1

T92

1

T321

1

auto[1]

from_1to0

auto[1]

auto[1]

34

1

T16

1

T69

2

T138

1

auto[1]

from_0to1

auto[0]

auto[0]

47

1

T16

1

T83

1

T92

1

auto[1]

from_0to1

auto[0]

auto[1]

43

1

T16

2

T69

1

T83

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T69

1

T83

1

T162

1

auto[1]

from_0to1

auto[1]

auto[1]

34

1

T69

1

T92

1

T101

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659

1

T16

10

T69

12

T83

11

auto[1]

654

1

T16

10

T69

8

T83

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

319

1

T16

5

T69

4

T83

7

from_0to1

318

1

T16

4

T69

4

T83

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

650

1

T16

10

T69

11

T83

8

auto[1]

663

1

T16

10

T69

9

T83

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

665

1

T16

6

T69

11

T83

13

auto[1]

648

1

T16

14

T69

9

T83

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

45

1

T69

1

T83

1

T92

1

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T83

1

T100

1

T145

3

auto[0]

from_1to0

auto[1]

auto[0]

33

1

T69

1

T321

1

T303

3

auto[0]

from_1to0

auto[1]

auto[1]

36

1

T16

1

T92

2

T162

1

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T83

1

T92

1

T162

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T16

1

T69

1

T100

1

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T69

1

T83

2

T92

1

auto[0]

from_0to1

auto[1]

auto[1]

30

1

T100

1

T303

1

T261

1

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T16

1

T69

1

T92

1

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T16

2

T162

1

T145

1

auto[1]

from_1to0

auto[1]

auto[0]

36

1

T83

2

T100

1

T321

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T16

1

T69

1

T83

3

auto[1]

from_0to1

auto[0]

auto[0]

33

1

T16

1

T83

1

T101

1

auto[1]

from_0to1

auto[0]

auto[1]

36

1

T69

1

T83

1

T162

2

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T16

1

T69

1

T83

1

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T16

1

T92

1

T100

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

682

1

T16

7

T69

11

T83

14

auto[1]

631

1

T16

13

T69

9

T83

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

317

1

T16

5

T69

4

T83

5

from_0to1

317

1

T16

5

T69

5

T83

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T16

5

T69

10

T83

6

auto[1]

671

1

T16

15

T69

10

T83

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

680

1

T16

10

T69

9

T83

12

auto[1]

633

1

T16

10

T69

11

T83

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T16

2

T92

1

T162

2

auto[0]

from_1to0

auto[0]

auto[1]

33

1

T83

1

T92

1

T100

1

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T69

1

T83

1

T162

2

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T16

2

T69

2

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T83

1

T162

2

T100

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T100

2

T138

1

T321

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T69

1

T83

1

T92

4

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T83

1

T162

1

T101

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T83

1

T92

1

T101

1

auto[1]

from_1to0

auto[0]

auto[1]

33

1

T92

1

T162

1

T303

1

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T69

1

T83

1

T100

2

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T16

1

T92

2

T101

3

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T83

1

T92

1

T100

1

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T16

1

T69

3

T83

1

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T16

3

T69

1

T162

1

auto[1]

from_0to1

auto[1]

auto[1]

35

1

T16

1

T162

1

T145

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T16

10

T69

10

T83

10

auto[1]

665

1

T16

10

T69

10

T83

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

310

1

T16

4

T69

6

T83

4

from_0to1

311

1

T16

4

T69

5

T83

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657

1

T16

9

T69

12

T83

7

auto[1]

656

1

T16

11

T69

8

T83

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

634

1

T16

8

T69

9

T83

7

auto[1]

679

1

T16

12

T69

11

T83

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T16

2

T92

1

T162

1

auto[0]

from_1to0

auto[0]

auto[1]

34

1

T69

1

T92

1

T162

1

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T16

1

T92

1

T162

1

auto[0]

from_1to0

auto[1]

auto[1]

28

1

T69

1

T83

1

T92

2

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T162

1

T100

2

T145

2

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T83

1

T101

1

T138

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T69

2

T83

1

T92

2

auto[0]

from_0to1

auto[1]

auto[1]

35

1

T16

1

T69

1

T101

1

auto[1]

from_1to0

auto[0]

auto[0]

40

1

T69

2

T83

2

T92

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T69

1

T138

1

T133

2

auto[1]

from_1to0

auto[1]

auto[0]

38

1

T83

1

T100

1

T145

1

auto[1]

from_1to0

auto[1]

auto[1]

45

1

T16

1

T69

1

T162

1

auto[1]

from_0to1

auto[0]

auto[0]

21

1

T16

1

T69

1

T162

1

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T16

1

T100

2

T101

1

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T16

1

T83

1

T92

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T69

1

T83

1

T92

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

670

1

T16

9

T69

9

T83

13

auto[1]

643

1

T16

11

T69

11

T83

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

321

1

T16

3

T69

5

T83

7

from_0to1

317

1

T16

4

T69

5

T83

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657

1

T16

7

T69

10

T83

12

auto[1]

656

1

T16

13

T69

10

T83

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

632

1

T16

9

T69

8

T83

12

auto[1]

681

1

T16

11

T69

12

T83

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

27

1

T83

2

T100

2

T101

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T69

1

T132

1

T133

1

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T16

1

T69

1

T83

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T16

2

T69

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

47

1

T16

1

T83

1

T92

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T69

2

T92

1

T101

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T69

1

T83

1

T92

1

auto[0]

from_0to1

auto[1]

auto[1]

44

1

T16

1

T69

1

T83

1

auto[1]

from_1to0

auto[0]

auto[0]

42

1

T69

1

T83

1

T162

1

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T101

1

T327

1

T132

2

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T69

1

T83

1

T162

2

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T83

1

T92

3

T101

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T92

1

T162

2

T327

1

auto[1]

from_0to1

auto[0]

auto[1]

37

1

T83

2

T100

1

T101

1

auto[1]

from_0to1

auto[1]

auto[0]

26

1

T16

1

T92

1

T100

1

auto[1]

from_0to1

auto[1]

auto[1]

36

1

T16

1

T69

1

T83

1