Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142098	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

111989

1

T4

15

T5

6

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	135733	1			T4	22		T5	12		T6	2
values[0x0]	58499	1			T4	12		T6	1		T23	18
values[0x1]	59855	1			T4	10		T23	14		T1	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	114510	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

139577

1

T4

20

T5

9

T6

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	913	1			T23	1		T11	1		T80	1
valid_sources[0x01]	825	1			T82	3		T87	1		T418	1
valid_sources[0x02]	856	1			T70	1		T82	2		T87	1
valid_sources[0x03]	639	1			T7	2		T80	1		T92	2
valid_sources[0x04]	964	1			T218	2		T28	2		T138	23
valid_sources[0x05]	971	1			T69	1		T80	2		T71	1
valid_sources[0x06]	869	1			T92	3		T87	2		T145	1
valid_sources[0x07]	787	1			T78	1		T87	1		T101	1
valid_sources[0x08]	788	1			T69	1		T78	1		T80	1
valid_sources[0x09]	797	1			T18	1		T68	1		T91	1
valid_sources[0x0a]	751	1			T293	13		T86	1		T190	1
valid_sources[0x0b]	1003	1			T23	6		T80	1		T87	1
valid_sources[0x0c]	1224	1			T31	1		T69	1		T82	1
valid_sources[0x0d]	959	1			T23	2		T31	2		T91	2
valid_sources[0x0e]	1282	1			T23	2		T19	60		T31	1
valid_sources[0x0f]	757	1			T23	5		T31	1		T69	1
valid_sources[0x10]	766	1			T69	1		T60	1		T82	1
valid_sources[0x11]	719	1			T5	12		T23	1		T91	2
valid_sources[0x12]	1000	1			T23	9		T31	1		T82	3
valid_sources[0x13]	760	1			T82	2		T220	1		T64	8
valid_sources[0x14]	943	1			T23	1		T18	1		T69	3
valid_sources[0x15]	762	1			T23	1		T87	1		T220	3
valid_sources[0x16]	673	1			T23	2		T17	1		T101	1
valid_sources[0x17]	839	1			T23	3		T69	1		T11	1
valid_sources[0x18]	801	1			T69	1		T82	1		T92	2
valid_sources[0x19]	907	1			T18	3		T30	7		T82	1
valid_sources[0x1a]	749	1			T82	2		T83	20		T13	1
valid_sources[0x1b]	995	1			T31	2		T80	2		T82	1
valid_sources[0x1c]	1954	1			T23	2		T16	123		T31	1
valid_sources[0x1d]	753	1			T23	5		T79	1		T82	1
valid_sources[0x1e]	939	1			T31	2		T11	2		T81	4
valid_sources[0x1f]	1001	1			T30	2		T69	3		T87	1
valid_sources[0x20]	910	1			T2	1		T71	3		T100	4
valid_sources[0x21]	1053	1			T18	1		T147	2		T86	3
valid_sources[0x22]	1744	1			T18	1		T31	2		T91	2
valid_sources[0x23]	762	1			T81	1		T101	5		T145	1
valid_sources[0x24]	915	1			T23	3		T32	1		T82	1
valid_sources[0x25]	1701	1			T23	1		T18	2		T69	1
valid_sources[0x26]	1115	1			T15	3		T69	1		T82	1
valid_sources[0x27]	910	1			T23	5		T3	1		T30	4
valid_sources[0x28]	661	1			T91	1		T87	1		T327	3
valid_sources[0x29]	933	1			T18	1		T82	4		T293	6
valid_sources[0x2a]	882	1			T7	4		T32	1		T78	4
valid_sources[0x2b]	937	1			T23	1		T2	1		T100	2
valid_sources[0x2c]	857	1			T80	1		T82	1		T83	7
valid_sources[0x2d]	1014	1			T31	1		T87	1		T101	1
valid_sources[0x2e]	909	1			T23	1		T18	1		T31	1
valid_sources[0x2f]	833	1			T69	1		T11	2		T78	2
valid_sources[0x30]	1152	1			T83	26		T87	1		T100	1
valid_sources[0x31]	839	1			T31	1		T80	1		T82	1
valid_sources[0x32]	866	1			T80	2		T82	2		T92	1
valid_sources[0x33]	844	1			T23	8		T68	1		T80	1
valid_sources[0x34]	712	1			T23	1		T32	3		T219	1
valid_sources[0x35]	849	1			T23	3		T69	4		T12	2
valid_sources[0x36]	1390	1			T17	1		T91	1		T80	1
valid_sources[0x37]	955	1			T23	1		T32	1		T52	21
valid_sources[0x38]	698	1			T68	1		T9	2		T82	2
valid_sources[0x39]	1032	1			T91	1		T87	2		T66	1
valid_sources[0x3a]	815	1			T23	1		T145	1		T418	1
valid_sources[0x3b]	954	1			T23	1		T18	1		T31	1
valid_sources[0x3c]	798	1			T23	4		T18	2		T31	2
valid_sources[0x3d]	780	1			T23	2		T91	2		T78	3
valid_sources[0x3e]	1479	1			T82	2		T145	2		T88	1
valid_sources[0x3f]	773	1			T18	6		T3	6		T82	1
valid_sources[0x40]	774	1			T23	1		T82	1		T145	2
valid_sources[0x41]	797	1			T8	16		T70	1		T91	1
valid_sources[0x42]	794	1			T71	1		T101	3		T88	1
valid_sources[0x43]	695	1			T23	1		T2	1		T69	4
valid_sources[0x44]	1873	1			T2	1		T70	1		T91	1
valid_sources[0x45]	2117	1			T2	1		T82	3		T220	4
valid_sources[0x46]	836	1			T18	1		T31	1		T80	2
valid_sources[0x47]	1127	1			T23	1		T69	1		T87	1
valid_sources[0x48]	910	1			T2	1		T7	1		T82	2
valid_sources[0x49]	1095	1			T18	1		T69	2		T78	2
valid_sources[0x4a]	773	1			T30	2		T101	2		T147	4
valid_sources[0x4b]	974	1			T69	3		T91	2		T82	4
valid_sources[0x4c]	921	1			T62	2		T87	2		T418	1
valid_sources[0x4d]	812	1			T23	2		T15	2		T69	1
valid_sources[0x4e]	898	1			T31	3		T87	2		T145	1
valid_sources[0x4f]	893	1			T18	1		T31	2		T68	1
valid_sources[0x50]	1824	1			T2	1		T80	1		T82	1
valid_sources[0x51]	1026	1			T31	1		T78	1		T82	1
valid_sources[0x52]	956	1			T23	2		T30	5		T91	1
valid_sources[0x53]	911	1			T23	1		T31	1		T80	1
valid_sources[0x54]	736	1			T23	2		T17	1		T69	3
valid_sources[0x55]	842	1			T23	1		T83	2		T99	5
valid_sources[0x56]	798	1			T18	1		T68	1		T80	1
valid_sources[0x57]	740	1			T69	1		T11	5		T78	1
valid_sources[0x58]	900	1			T23	3		T7	4		T82	2
valid_sources[0x59]	920	1			T31	1		T69	3		T145	1
valid_sources[0x5a]	1033	1			T23	1		T92	1		T87	2
valid_sources[0x5b]	864	1			T82	3		T83	15		T50	1
valid_sources[0x5c]	1314	1			T70	1		T82	4		T87	1
valid_sources[0x5d]	1863	1			T80	1		T83	9		T71	1
valid_sources[0x5e]	1716	1			T92	2		T220	1		T101	2
valid_sources[0x5f]	604	1			T23	2		T145	2		T66	1
valid_sources[0x60]	876	1			T87	1		T101	1		T50	1
valid_sources[0x61]	1136	1			T23	1		T3	4		T31	1
valid_sources[0x62]	1802	1			T23	1		T82	2		T87	1
valid_sources[0x63]	749	1			T31	1		T82	3		T138	1
valid_sources[0x64]	693	1			T83	8		T13	2		T92	2
valid_sources[0x65]	786	1			T69	1		T11	4		T87	1
valid_sources[0x66]	1083	1			T69	2		T32	1		T82	1
valid_sources[0x67]	859	1			T23	1		T31	1		T91	1
valid_sources[0x68]	834	1			T220	3		T86	2		T136	1
valid_sources[0x69]	1254	1			T63	1		T86	2		T136	3
valid_sources[0x6a]	902	1			T91	2		T62	1		T145	1
valid_sources[0x6b]	913	1			T23	3		T82	3		T220	3
valid_sources[0x6c]	939	1			T23	1		T31	1		T91	1
valid_sources[0x6d]	1935	1			T23	5		T18	1		T31	1
valid_sources[0x6e]	735	1			T23	2		T79	1		T82	3
valid_sources[0x6f]	981	1			T18	1		T69	3		T293	4
valid_sources[0x70]	856	1			T82	2		T83	118		T13	1
valid_sources[0x71]	616	1			T23	1		T18	2		T31	1
valid_sources[0x72]	815	1			T10	78		T92	2		T138	7
valid_sources[0x73]	1194	1			T4	9		T69	6		T87	1
valid_sources[0x74]	937	1			T4	2		T23	2		T20	10
valid_sources[0x75]	755	1			T101	1		T50	1		T327	8
valid_sources[0x76]	759	1			T72	26		T418	3		T329	9
valid_sources[0x77]	737	1			T23	3		T17	1		T91	1
valid_sources[0x78]	1298	1			T23	1		T30	7		T82	2
valid_sources[0x79]	798	1			T2	1		T82	1		T101	4
valid_sources[0x7a]	747	1			T83	18		T165	1		T71	1
valid_sources[0x7b]	1429	1			T23	2		T69	2		T92	4
valid_sources[0x7c]	840	1			T4	4		T1	1		T2	1
valid_sources[0x7d]	820	1			T23	1		T69	3		T145	3
valid_sources[0x7e]	855	1			T23	2		T18	1		T69	4
valid_sources[0x7f]	738	1			T92	9		T145	1		T88	3
valid_sources[0x80]	1284	1			T83	20		T92	1		T33	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61796

1

T4

6

T5

6

T6

1

values[0x0]

all_enables

biggest_size

29129

1

T4

7

T23

18

T1

4

values[0x1]

all_enables

biggest_size

21064

1

T4

2

T23

11

T15

2