Unified Coverage Report :: Module :: sysrst_ctrl_comboact

Module : sysrst_ctrl_comboact

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act	99.19	100.00	97.56			100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act	99.19	100.00	97.56			100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act	99.19	100.00	97.56			100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act	99.19	100.00	97.56			100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : sysrst_ctrl_comboact

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

33                        logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse;
34         1/1            assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i;
           Tests:       T1 T3 T9 
35         1/1            assign combo_ec_rst_pulse      = cfg_ec_rst_en_i & combo_det_pulse_i;
           Tests:       T1 T15 T17 
36         1/1            assign combo_ot_pulse         = cfg_rst_req_en_i & combo_det_pulse_i;
           Tests:       T1 T3 T9 
37         1/1            assign combo_intr_pulse_o      = cfg_intr_en_i & combo_det_pulse_i;
           Tests:       T1 T15 T17 
38                      
39                        //ec_rst_l_i high->low detection
40                        logic ec_rst_l_det_pulse, ec_rst_l_det_q;
41         1/1            assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q;
           Tests:       T4 T5 T6 
42                      
43                        ////////////////////////////////////
44                        // Bat / OT reset pulse latching //
45                        ////////////////////////////////////
46                      
47                        logic bat_disable_q, bat_disable_d;
48         1/1            assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse;
           Tests:       T57 T58 T48 
49         1/1            assign bat_disable_o = bat_disable_q;
           Tests:       T57 T58 T48 
50                      
51                        logic rst_req_q, rst_req_d;
52         1/1            assign rst_req_d = rst_req_q | combo_ot_pulse;
           Tests:       T35 T59 T49 
53         1/1            assign rst_req_o = rst_req_q;
           Tests:       T35 T59 T49 
54                      
55                        ////////////////////
56                        // EC reset logic //
57                        ////////////////////
58                      
59                        // OT reset will also reset EC
60                        logic timer_expired;
61                        logic ec_rst_l_q, ec_rst_l_d;
62         1/1            assign ec_rst_l_o = ec_rst_l_q;
           Tests:       T1 T15 T17 
63         1/1            assign ec_rst_l_d = (combo_ec_rst_pulse ||
           Tests:       T4 T5 T6 
64                                             ec_rst_l_det_pulse) ? 1'b0 :
65                                            (timer_expired)      ? 1'b1 : ec_rst_l_q;
66                      
67                      
68                        // Reset stretching counter
69                        logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
70         1/1            assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
           Tests:       T4 T5 T6 
71         1/1            assign timer_cnt_d = (timer_expired)       ? '0                 :
           Tests:       T4 T5 T6 
72                                             (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
73                      
74                        ///////////////
75                        // Registers //
76                        ///////////////
77                      
78                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
79         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
80         1/1                bat_disable_q  <= 1'b0;
           Tests:       T4 T5 T6 
81         1/1                ec_rst_l_det_q <= 1'b1;  // active low signal
           Tests:       T4 T5 T6 
82         1/1                rst_req_q      <= 1'b0;
           Tests:       T4 T5 T6 
83         1/1                ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
           Tests:       T4 T5 T6 
84         1/1                timer_cnt_q    <= '0;
           Tests:       T4 T5 T6 
85                          end else begin
86         1/1                bat_disable_q  <= bat_disable_d;
           Tests:       T4 T5 T6 
87         1/1                ec_rst_l_det_q <= ec_rst_l_i;
           Tests:       T4 T5 T6 
88         1/1                rst_req_q      <= rst_req_d;
           Tests:       T4 T5 T6 
89         1/1                ec_rst_l_q     <= ec_rst_l_d;
           Tests:       T4 T5 T6 
90         1/1                timer_cnt_q    <= timer_cnt_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : sysrst_ctrl_comboact

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T35,T46,T57
1	1	Covered	T57,T58,T48

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T46,T59,T49
1	0	Covered	T1,T15,T17
1	1	Covered	T1,T3,T9

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T35,T46,T59
1	1	Covered	T35,T59,T49

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T1,T15,T17
1	1	Covered	T1,T3,T9

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T57,T58,T48
1	0	Covered	T57,T58,T48

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T35,T59,T49
1	0	Covered	T35,T59,T49

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T9

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T15,T17

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

---

Branch Coverage for Module : sysrst_ctrl_comboact

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

63           assign ec_rst_l_d = (combo_ec_rst_pulse ||
                                                       
64                                ec_rst_l_det_pulse) ? 1'b0 :
                                                      -1-  
                                                      ==>  
65                               (timer_expired)      ? 1'b1 : ec_rst_l_q;
                                                      -2-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T15,T17
0	0	Covered	T4,T5,T6

71           assign timer_cnt_d = (timer_expired)       ? '0                 :
                                                        -1-  
                                                        ==>  
72                                (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
                                                        -2-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T17
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T15,T17

79             if (!rst_ni) begin
               -1-  
80               bat_disable_q  <= 1'b0;
                 ==>
81               ec_rst_l_det_q <= 1'b1;  // active low signal
82               rst_req_q      <= 1'b0;
83               ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
84               timer_cnt_q    <= '0;
85             end else begin
86               bat_disable_q  <= bat_disable_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

33                        logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse;
34         1/1            assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i;
           Tests:       T1 T3 T9 
35         1/1            assign combo_ec_rst_pulse      = cfg_ec_rst_en_i & combo_det_pulse_i;
           Tests:       T1 T15 T17 
36         1/1            assign combo_ot_pulse         = cfg_rst_req_en_i & combo_det_pulse_i;
           Tests:       T1 T3 T9 
37         1/1            assign combo_intr_pulse_o      = cfg_intr_en_i & combo_det_pulse_i;
           Tests:       T1 T15 T17 
38                      
39                        //ec_rst_l_i high->low detection
40                        logic ec_rst_l_det_pulse, ec_rst_l_det_q;
41         1/1            assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q;
           Tests:       T4 T5 T6 
42                      
43                        ////////////////////////////////////
44                        // Bat / OT reset pulse latching //
45                        ////////////////////////////////////
46                      
47                        logic bat_disable_q, bat_disable_d;
48         1/1            assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse;
           Tests:       T57 T43 T44 
49         1/1            assign bat_disable_o = bat_disable_q;
           Tests:       T57 T43 T44 
50                      
51                        logic rst_req_q, rst_req_d;
52         1/1            assign rst_req_d = rst_req_q | combo_ot_pulse;
           Tests:       T49 T57 T48 
53         1/1            assign rst_req_o = rst_req_q;
           Tests:       T49 T57 T48 
54                      
55                        ////////////////////
56                        // EC reset logic //
57                        ////////////////////
58                      
59                        // OT reset will also reset EC
60                        logic timer_expired;
61                        logic ec_rst_l_q, ec_rst_l_d;
62         1/1            assign ec_rst_l_o = ec_rst_l_q;
           Tests:       T1 T15 T17 
63         1/1            assign ec_rst_l_d = (combo_ec_rst_pulse ||
           Tests:       T4 T5 T6 
64                                             ec_rst_l_det_pulse) ? 1'b0 :
65                                            (timer_expired)      ? 1'b1 : ec_rst_l_q;
66                      
67                      
68                        // Reset stretching counter
69                        logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
70         1/1            assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
           Tests:       T4 T5 T6 
71         1/1            assign timer_cnt_d = (timer_expired)       ? '0                 :
           Tests:       T4 T5 T6 
72                                             (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
73                      
74                        ///////////////
75                        // Registers //
76                        ///////////////
77                      
78                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
79         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
80         1/1                bat_disable_q  <= 1'b0;
           Tests:       T4 T5 T6 
81         1/1                ec_rst_l_det_q <= 1'b1;  // active low signal
           Tests:       T4 T5 T6 
82         1/1                rst_req_q      <= 1'b0;
           Tests:       T4 T5 T6 
83         1/1                ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
           Tests:       T4 T5 T6 
84         1/1                timer_cnt_q    <= '0;
           Tests:       T4 T5 T6 
85                          end else begin
86         1/1                bat_disable_q  <= bat_disable_d;
           Tests:       T4 T5 T6 
87         1/1                ec_rst_l_det_q <= ec_rst_l_i;
           Tests:       T4 T5 T6 
88         1/1                rst_req_q      <= rst_req_d;
           Tests:       T4 T5 T6 
89         1/1                ec_rst_l_q     <= ec_rst_l_d;
           Tests:       T4 T5 T6 
90         1/1                timer_cnt_q    <= timer_cnt_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T35,T57,T96
1	1	Covered	T57,T43,T44

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T49,T48,T45
1	0	Covered	T1,T15,T17
1	1	Covered	T1,T3,T9

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T46,T59,T49
1	1	Covered	T49,T57,T48

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T36,T49
1	0	Covered	T1,T15,T17
1	1	Covered	T1,T3,T9

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T57,T43,T44
1	0	Covered	T57,T43,T44

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T49,T57,T48
1	0	Covered	T49,T57,T48

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T9

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T15,T17

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

63           assign ec_rst_l_d = (combo_ec_rst_pulse ||
                                                       
64                                ec_rst_l_det_pulse) ? 1'b0 :
                                                      -1-  
                                                      ==>  
65                               (timer_expired)      ? 1'b1 : ec_rst_l_q;
                                                      -2-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T15,T17
0	0	Covered	T4,T5,T6

71           assign timer_cnt_d = (timer_expired)       ? '0                 :
                                                        -1-  
                                                        ==>  
72                                (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
                                                        -2-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T17
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T15,T17

79             if (!rst_ni) begin
               -1-  
80               bat_disable_q  <= 1'b0;
                 ==>
81               ec_rst_l_det_q <= 1'b1;  // active low signal
82               rst_req_q      <= 1'b0;
83               ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
84               timer_cnt_q    <= '0;
85             end else begin
86               bat_disable_q  <= bat_disable_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

33                        logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse;
34         1/1            assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
35         1/1            assign combo_ec_rst_pulse      = cfg_ec_rst_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
36         1/1            assign combo_ot_pulse         = cfg_rst_req_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
37         1/1            assign combo_intr_pulse_o      = cfg_intr_en_i & combo_det_pulse_i;
           Tests:       T34 T36 T46 
38                      
39                        //ec_rst_l_i high->low detection
40                        logic ec_rst_l_det_pulse, ec_rst_l_det_q;
41         1/1            assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q;
           Tests:       T4 T5 T6 
42                      
43                        ////////////////////////////////////
44                        // Bat / OT reset pulse latching //
45                        ////////////////////////////////////
46                      
47                        logic bat_disable_q, bat_disable_d;
48         1/1            assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse;
           Tests:       T57 T97 T43 
49         1/1            assign bat_disable_o = bat_disable_q;
           Tests:       T57 T97 T43 
50                      
51                        logic rst_req_q, rst_req_d;
52         1/1            assign rst_req_d = rst_req_q | combo_ot_pulse;
           Tests:       T59 T97 T43 
53         1/1            assign rst_req_o = rst_req_q;
           Tests:       T59 T97 T43 
54                      
55                        ////////////////////
56                        // EC reset logic //
57                        ////////////////////
58                      
59                        // OT reset will also reset EC
60                        logic timer_expired;
61                        logic ec_rst_l_q, ec_rst_l_d;
62         1/1            assign ec_rst_l_o = ec_rst_l_q;
           Tests:       T1 T15 T17 
63         1/1            assign ec_rst_l_d = (combo_ec_rst_pulse ||
           Tests:       T4 T5 T6 
64                                             ec_rst_l_det_pulse) ? 1'b0 :
65                                            (timer_expired)      ? 1'b1 : ec_rst_l_q;
66                      
67                      
68                        // Reset stretching counter
69                        logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
70         1/1            assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
           Tests:       T4 T5 T6 
71         1/1            assign timer_cnt_d = (timer_expired)       ? '0                 :
           Tests:       T4 T5 T6 
72                                             (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
73                      
74                        ///////////////
75                        // Registers //
76                        ///////////////
77                      
78                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
79         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
80         1/1                bat_disable_q  <= 1'b0;
           Tests:       T4 T5 T6 
81         1/1                ec_rst_l_det_q <= 1'b1;  // active low signal
           Tests:       T4 T5 T6 
82         1/1                rst_req_q      <= 1'b0;
           Tests:       T4 T5 T6 
83         1/1                ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
           Tests:       T4 T5 T6 
84         1/1                timer_cnt_q    <= '0;
           Tests:       T4 T5 T6 
85                          end else begin
86         1/1                bat_disable_q  <= bat_disable_d;
           Tests:       T4 T5 T6 
87         1/1                ec_rst_l_det_q <= ec_rst_l_i;
           Tests:       T4 T5 T6 
88         1/1                rst_req_q      <= rst_req_d;
           Tests:       T4 T5 T6 
89         1/1                ec_rst_l_q     <= ec_rst_l_d;
           Tests:       T4 T5 T6 
90         1/1                timer_cnt_q    <= timer_cnt_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T36,T59
1	0	Covered	T35,T57,T58
1	1	Covered	T57,T97,T43

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T59,T103,T43
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T36,T57

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T36,T57
1	0	Covered	T35,T46,T59
1	1	Covered	T59,T97,T43

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T36,T59
1	0	Covered	T46,T49,T47
1	1	Covered	T43,T44,T45

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T57,T97,T43
1	0	Covered	T57,T97,T43

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T59,T97,T43
1	0	Covered	T59,T97,T43

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T34,T36,T57

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T15,T17

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

63           assign ec_rst_l_d = (combo_ec_rst_pulse ||
                                                       
64                                ec_rst_l_det_pulse) ? 1'b0 :
                                                      -1-  
                                                      ==>  
65                               (timer_expired)      ? 1'b1 : ec_rst_l_q;
                                                      -2-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T15,T17
0	0	Covered	T4,T5,T6

71           assign timer_cnt_d = (timer_expired)       ? '0                 :
                                                        -1-  
                                                        ==>  
72                                (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
                                                        -2-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T17
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T15,T17

79             if (!rst_ni) begin
               -1-  
80               bat_disable_q  <= 1'b0;
                 ==>
81               ec_rst_l_det_q <= 1'b1;  // active low signal
82               rst_req_q      <= 1'b0;
83               ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
84               timer_cnt_q    <= '0;
85             end else begin
86               bat_disable_q  <= bat_disable_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

33                        logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse;
34         1/1            assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
35         1/1            assign combo_ec_rst_pulse      = cfg_ec_rst_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
36         1/1            assign combo_ot_pulse         = cfg_rst_req_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
37         1/1            assign combo_intr_pulse_o      = cfg_intr_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
38                      
39                        //ec_rst_l_i high->low detection
40                        logic ec_rst_l_det_pulse, ec_rst_l_det_q;
41         1/1            assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q;
           Tests:       T4 T5 T6 
42                      
43                        ////////////////////////////////////
44                        // Bat / OT reset pulse latching //
45                        ////////////////////////////////////
46                      
47                        logic bat_disable_q, bat_disable_d;
48         1/1            assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse;
           Tests:       T57 T58 T48 
49         1/1            assign bat_disable_o = bat_disable_q;
           Tests:       T57 T58 T48 
50                      
51                        logic rst_req_q, rst_req_d;
52         1/1            assign rst_req_d = rst_req_q | combo_ot_pulse;
           Tests:       T35 T118 T43 
53         1/1            assign rst_req_o = rst_req_q;
           Tests:       T35 T118 T43 
54                      
55                        ////////////////////
56                        // EC reset logic //
57                        ////////////////////
58                      
59                        // OT reset will also reset EC
60                        logic timer_expired;
61                        logic ec_rst_l_q, ec_rst_l_d;
62         1/1            assign ec_rst_l_o = ec_rst_l_q;
           Tests:       T1 T15 T17 
63         1/1            assign ec_rst_l_d = (combo_ec_rst_pulse ||
           Tests:       T4 T5 T6 
64                                             ec_rst_l_det_pulse) ? 1'b0 :
65                                            (timer_expired)      ? 1'b1 : ec_rst_l_q;
66                      
67                      
68                        // Reset stretching counter
69                        logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
70         1/1            assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
           Tests:       T4 T5 T6 
71         1/1            assign timer_cnt_d = (timer_expired)       ? '0                 :
           Tests:       T4 T5 T6 
72                                             (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
73                      
74                        ///////////////
75                        // Registers //
76                        ///////////////
77                      
78                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
79         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
80         1/1                bat_disable_q  <= 1'b0;
           Tests:       T4 T5 T6 
81         1/1                ec_rst_l_det_q <= 1'b1;  // active low signal
           Tests:       T4 T5 T6 
82         1/1                rst_req_q      <= 1'b0;
           Tests:       T4 T5 T6 
83         1/1                ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
           Tests:       T4 T5 T6 
84         1/1                timer_cnt_q    <= '0;
           Tests:       T4 T5 T6 
85                          end else begin
86         1/1                bat_disable_q  <= bat_disable_d;
           Tests:       T4 T5 T6 
87         1/1                ec_rst_l_det_q <= ec_rst_l_i;
           Tests:       T4 T5 T6 
88         1/1                rst_req_q      <= rst_req_d;
           Tests:       T4 T5 T6 
89         1/1                ec_rst_l_q     <= ec_rst_l_d;
           Tests:       T4 T5 T6 
90         1/1                timer_cnt_q    <= timer_cnt_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T57,T58,T48
1	1	Covered	T57,T58,T48

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T46,T59,T58
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T36,T46
1	0	Covered	T35,T96,T118
1	1	Covered	T35,T118,T43

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T46,T96,T47
1	1	Covered	T46,T47,T48

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T57,T58,T48
1	0	Covered	T57,T58,T48

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T35,T118,T43
1	0	Covered	T35,T118,T43

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T34,T35,T36

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T15,T17

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

63           assign ec_rst_l_d = (combo_ec_rst_pulse ||
                                                       
64                                ec_rst_l_det_pulse) ? 1'b0 :
                                                      -1-  
                                                      ==>  
65                               (timer_expired)      ? 1'b1 : ec_rst_l_q;
                                                      -2-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T15,T17
0	0	Covered	T4,T5,T6

71           assign timer_cnt_d = (timer_expired)       ? '0                 :
                                                        -1-  
                                                        ==>  
72                                (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
                                                        -2-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T17
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T15,T17

79             if (!rst_ni) begin
               -1-  
80               bat_disable_q  <= 1'b0;
                 ==>
81               ec_rst_l_det_q <= 1'b1;  // active low signal
82               rst_req_q      <= 1'b0;
83               ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
84               timer_cnt_q    <= '0;
85             end else begin
86               bat_disable_q  <= bat_disable_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

33                        logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse;
34         1/1            assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
35         1/1            assign combo_ec_rst_pulse      = cfg_ec_rst_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
36         1/1            assign combo_ot_pulse         = cfg_rst_req_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
37         1/1            assign combo_intr_pulse_o      = cfg_intr_en_i & combo_det_pulse_i;
           Tests:       T34 T35 T36 
38                      
39                        //ec_rst_l_i high->low detection
40                        logic ec_rst_l_det_pulse, ec_rst_l_det_q;
41         1/1            assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q;
           Tests:       T4 T5 T6 
42                      
43                        ////////////////////////////////////
44                        // Bat / OT reset pulse latching //
45                        ////////////////////////////////////
46                      
47                        logic bat_disable_q, bat_disable_d;
48         1/1            assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse;
           Tests:       T46 T48 T118 
49         1/1            assign bat_disable_o = bat_disable_q;
           Tests:       T46 T48 T118 
50                      
51                        logic rst_req_q, rst_req_d;
52         1/1            assign rst_req_d = rst_req_q | combo_ot_pulse;
           Tests:       T46 T48 T97 
53         1/1            assign rst_req_o = rst_req_q;
           Tests:       T46 T48 T97 
54                      
55                        ////////////////////
56                        // EC reset logic //
57                        ////////////////////
58                      
59                        // OT reset will also reset EC
60                        logic timer_expired;
61                        logic ec_rst_l_q, ec_rst_l_d;
62         1/1            assign ec_rst_l_o = ec_rst_l_q;
           Tests:       T1 T15 T17 
63         1/1            assign ec_rst_l_d = (combo_ec_rst_pulse ||
           Tests:       T4 T5 T6 
64                                             ec_rst_l_det_pulse) ? 1'b0 :
65                                            (timer_expired)      ? 1'b1 : ec_rst_l_q;
66                      
67                      
68                        // Reset stretching counter
69                        logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
70         1/1            assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
           Tests:       T4 T5 T6 
71         1/1            assign timer_cnt_d = (timer_expired)       ? '0                 :
           Tests:       T4 T5 T6 
72                                             (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
73                      
74                        ///////////////
75                        // Registers //
76                        ///////////////
77                      
78                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
79         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
80         1/1                bat_disable_q  <= 1'b0;
           Tests:       T4 T5 T6 
81         1/1                ec_rst_l_det_q <= 1'b1;  // active low signal
           Tests:       T4 T5 T6 
82         1/1                rst_req_q      <= 1'b0;
           Tests:       T4 T5 T6 
83         1/1                ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
           Tests:       T4 T5 T6 
84         1/1                timer_cnt_q    <= '0;
           Tests:       T4 T5 T6 
85                          end else begin
86         1/1                bat_disable_q  <= bat_disable_d;
           Tests:       T4 T5 T6 
87         1/1                ec_rst_l_det_q <= ec_rst_l_i;
           Tests:       T4 T5 T6 
88         1/1                rst_req_q      <= rst_req_d;
           Tests:       T4 T5 T6 
89         1/1                ec_rst_l_q     <= ec_rst_l_d;
           Tests:       T4 T5 T6 
90         1/1                timer_cnt_q    <= timer_cnt_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T36,T59
1	0	Covered	T35,T46,T48
1	1	Covered	T46,T48,T118

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T46,T49,T57
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T36,T59

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T36,T59
1	0	Covered	T35,T46,T48
1	1	Covered	T46,T48,T97

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T36,T46
1	0	Covered	T35,T49,T96
1	1	Covered	T49,T47,T48

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T46,T48,T118
1	0	Covered	T46,T48,T118

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T46,T48,T97
1	0	Covered	T46,T48,T97

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T34,T36,T59

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T15,T17

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

63           assign ec_rst_l_d = (combo_ec_rst_pulse ||
                                                       
64                                ec_rst_l_det_pulse) ? 1'b0 :
                                                      -1-  
                                                      ==>  
65                               (timer_expired)      ? 1'b1 : ec_rst_l_q;
                                                      -2-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T15,T17
0	0	Covered	T4,T5,T6

71           assign timer_cnt_d = (timer_expired)       ? '0                 :
                                                        -1-  
                                                        ==>  
72                                (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
                                                        -2-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T17
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T15,T17

79             if (!rst_ni) begin
               -1-  
80               bat_disable_q  <= 1'b0;
                 ==>
81               ec_rst_l_det_q <= 1'b1;  // active low signal
82               rst_req_q      <= 1'b0;
83               ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
84               timer_cnt_q    <= '0;
85             end else begin
86               bat_disable_q  <= bat_disable_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6