| T479 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.911115951 |
|
|
Sep 01 09:04:19 AM UTC 24 |
Sep 01 09:06:15 AM UTC 24 |
36992284592 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.973789974 |
|
|
Sep 01 09:04:23 AM UTC 24 |
Sep 01 09:06:16 AM UTC 24 |
426312891907 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.306583697 |
|
|
Sep 01 09:05:57 AM UTC 24 |
Sep 01 09:06:16 AM UTC 24 |
17790597612 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3226965131 |
|
|
Sep 01 09:04:57 AM UTC 24 |
Sep 01 09:06:17 AM UTC 24 |
157738978578 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2051399503 |
|
|
Sep 01 09:06:07 AM UTC 24 |
Sep 01 09:06:17 AM UTC 24 |
2015004966 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.3433659150 |
|
|
Sep 01 09:06:14 AM UTC 24 |
Sep 01 09:06:18 AM UTC 24 |
3186694396 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.3241705172 |
|
|
Sep 01 09:06:05 AM UTC 24 |
Sep 01 09:06:18 AM UTC 24 |
3312281359 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.454157751 |
|
|
Sep 01 09:06:37 AM UTC 24 |
Sep 01 09:06:45 AM UTC 24 |
2111574339 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.109495099 |
|
|
Sep 01 09:05:34 AM UTC 24 |
Sep 01 09:06:18 AM UTC 24 |
28356562619 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.175688549 |
|
|
Sep 01 09:06:06 AM UTC 24 |
Sep 01 09:06:19 AM UTC 24 |
2722551537 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.3603296673 |
|
|
Sep 01 09:06:08 AM UTC 24 |
Sep 01 09:06:21 AM UTC 24 |
2443097118 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.4243080434 |
|
|
Sep 01 09:06:11 AM UTC 24 |
Sep 01 09:06:21 AM UTC 24 |
2614766567 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.1765644388 |
|
|
Sep 01 09:06:18 AM UTC 24 |
Sep 01 09:06:21 AM UTC 24 |
2489587809 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.3027599254 |
|
|
Sep 01 09:06:18 AM UTC 24 |
Sep 01 09:06:22 AM UTC 24 |
2134795020 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.75257252 |
|
|
Sep 01 09:06:13 AM UTC 24 |
Sep 01 09:06:23 AM UTC 24 |
2908071312 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.1739593027 |
|
|
Sep 01 09:06:17 AM UTC 24 |
Sep 01 09:06:24 AM UTC 24 |
2014621000 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1246662006 |
|
|
Sep 01 09:06:19 AM UTC 24 |
Sep 01 09:06:26 AM UTC 24 |
2619375436 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3676775737 |
|
|
Sep 01 09:04:32 AM UTC 24 |
Sep 01 09:06:26 AM UTC 24 |
145645906407 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.3734091372 |
|
|
Sep 01 09:06:19 AM UTC 24 |
Sep 01 09:06:27 AM UTC 24 |
2513560935 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3971682467 |
|
|
Sep 01 09:06:11 AM UTC 24 |
Sep 01 09:06:27 AM UTC 24 |
3734399109 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3839984669 |
|
|
Sep 01 09:05:57 AM UTC 24 |
Sep 01 09:06:29 AM UTC 24 |
14565824708 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.2667896178 |
|
|
Sep 01 09:06:19 AM UTC 24 |
Sep 01 09:06:30 AM UTC 24 |
2096460317 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1697165071 |
|
|
Sep 01 09:06:22 AM UTC 24 |
Sep 01 09:06:31 AM UTC 24 |
5381788061 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3758832158 |
|
|
Sep 01 09:06:11 AM UTC 24 |
Sep 01 09:06:31 AM UTC 24 |
3924875315 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.436543073 |
|
|
Sep 01 09:06:27 AM UTC 24 |
Sep 01 09:06:31 AM UTC 24 |
2137081242 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1058057507 |
|
|
Sep 01 09:06:16 AM UTC 24 |
Sep 01 09:06:32 AM UTC 24 |
5493397427 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3165168390 |
|
|
Sep 01 09:06:28 AM UTC 24 |
Sep 01 09:06:32 AM UTC 24 |
2480695081 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2085549123 |
|
|
Sep 01 09:06:21 AM UTC 24 |
Sep 01 09:06:32 AM UTC 24 |
3346042462 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.202936513 |
|
|
Sep 01 09:06:28 AM UTC 24 |
Sep 01 09:06:32 AM UTC 24 |
2086217875 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.1280374866 |
|
|
Sep 01 09:04:15 AM UTC 24 |
Sep 01 09:06:33 AM UTC 24 |
135050002990 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1116725521 |
|
|
Sep 01 09:06:19 AM UTC 24 |
Sep 01 09:06:36 AM UTC 24 |
2975026497 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2758345591 |
|
|
Sep 01 09:06:31 AM UTC 24 |
Sep 01 09:06:36 AM UTC 24 |
4009378130 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.1771267432 |
|
|
Sep 01 09:06:27 AM UTC 24 |
Sep 01 09:06:36 AM UTC 24 |
2012165824 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3824981263 |
|
|
Sep 01 09:06:31 AM UTC 24 |
Sep 01 09:06:37 AM UTC 24 |
2633428528 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2914092448 |
|
|
Sep 01 09:06:32 AM UTC 24 |
Sep 01 09:06:37 AM UTC 24 |
3321380461 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.386955260 |
|
|
Sep 01 09:06:31 AM UTC 24 |
Sep 01 09:06:38 AM UTC 24 |
3984395054 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1043656265 |
|
|
Sep 01 09:06:37 AM UTC 24 |
Sep 01 09:06:40 AM UTC 24 |
2045131821 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4134413754 |
|
|
Sep 01 09:04:23 AM UTC 24 |
Sep 01 09:06:40 AM UTC 24 |
42988854007 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.373949831 |
|
|
Sep 01 09:06:37 AM UTC 24 |
Sep 01 09:06:41 AM UTC 24 |
2502690888 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.2075864352 |
|
|
Sep 01 09:06:38 AM UTC 24 |
Sep 01 09:06:42 AM UTC 24 |
2534857190 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.1131383674 |
|
|
Sep 01 09:06:29 AM UTC 24 |
Sep 01 09:06:43 AM UTC 24 |
2511536136 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3517340332 |
|
|
Sep 01 09:06:34 AM UTC 24 |
Sep 01 09:06:44 AM UTC 24 |
3551282556 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.2935957782 |
|
|
Sep 01 09:06:38 AM UTC 24 |
Sep 01 09:06:45 AM UTC 24 |
2263501125 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3952778554 |
|
|
Sep 01 09:06:39 AM UTC 24 |
Sep 01 09:06:45 AM UTC 24 |
2614644515 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3221957552 |
|
|
Sep 01 09:06:25 AM UTC 24 |
Sep 01 09:06:45 AM UTC 24 |
13825486971 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.331353117 |
|
|
Sep 01 09:06:41 AM UTC 24 |
Sep 01 09:06:45 AM UTC 24 |
3270834988 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.564818188 |
|
|
Sep 01 09:06:33 AM UTC 24 |
Sep 01 09:06:46 AM UTC 24 |
4584148455 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3526071614 |
|
|
Sep 01 09:06:40 AM UTC 24 |
Sep 01 09:06:46 AM UTC 24 |
3375384091 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.2631325051 |
|
|
Sep 01 09:05:19 AM UTC 24 |
Sep 01 09:06:47 AM UTC 24 |
111475730700 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.1407871780 |
|
|
Sep 01 09:06:46 AM UTC 24 |
Sep 01 09:06:50 AM UTC 24 |
2036947126 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1493071390 |
|
|
Sep 01 09:06:25 AM UTC 24 |
Sep 01 09:06:52 AM UTC 24 |
6783864702 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.2561195603 |
|
|
Sep 01 09:06:47 AM UTC 24 |
Sep 01 09:06:52 AM UTC 24 |
2536055629 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.2010194837 |
|
|
Sep 01 09:07:33 AM UTC 24 |
Sep 01 09:07:39 AM UTC 24 |
5613288563 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.2136880834 |
|
|
Sep 01 09:06:46 AM UTC 24 |
Sep 01 09:06:53 AM UTC 24 |
2116627452 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.589979859 |
|
|
Sep 01 09:06:47 AM UTC 24 |
Sep 01 09:06:53 AM UTC 24 |
2616039233 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.1331206589 |
|
|
Sep 01 09:06:46 AM UTC 24 |
Sep 01 09:06:54 AM UTC 24 |
2457220211 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.988648050 |
|
|
Sep 01 09:06:42 AM UTC 24 |
Sep 01 09:06:55 AM UTC 24 |
6151481186 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.408703609 |
|
|
Sep 01 09:06:48 AM UTC 24 |
Sep 01 09:06:55 AM UTC 24 |
4832396717 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.58999242 |
|
|
Sep 01 09:06:45 AM UTC 24 |
Sep 01 09:06:55 AM UTC 24 |
6425726183 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.2867374944 |
|
|
Sep 01 09:06:45 AM UTC 24 |
Sep 01 09:06:55 AM UTC 24 |
3374973956 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3778466959 |
|
|
Sep 01 09:06:46 AM UTC 24 |
Sep 01 09:06:56 AM UTC 24 |
2114694037 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.2512120187 |
|
|
Sep 01 09:06:13 AM UTC 24 |
Sep 01 09:06:57 AM UTC 24 |
52228356549 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.257811770 |
|
|
Sep 01 09:06:56 AM UTC 24 |
Sep 01 09:07:00 AM UTC 24 |
2485924946 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.2039957457 |
|
|
Sep 01 09:06:57 AM UTC 24 |
Sep 01 09:07:02 AM UTC 24 |
2538222682 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1164116824 |
|
|
Sep 01 09:06:50 AM UTC 24 |
Sep 01 09:07:02 AM UTC 24 |
3088175074 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3853153260 |
|
|
Sep 01 09:06:53 AM UTC 24 |
Sep 01 09:07:02 AM UTC 24 |
11697081429 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.2673533172 |
|
|
Sep 01 09:06:56 AM UTC 24 |
Sep 01 09:07:03 AM UTC 24 |
2145401718 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.465444327 |
|
|
Sep 01 09:06:58 AM UTC 24 |
Sep 01 09:07:04 AM UTC 24 |
2627034553 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2637326788 |
|
|
Sep 01 09:06:54 AM UTC 24 |
Sep 01 09:07:06 AM UTC 24 |
2423802589 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.357551294 |
|
|
Sep 01 09:05:04 AM UTC 24 |
Sep 01 09:07:06 AM UTC 24 |
162238916347 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.3984549793 |
|
|
Sep 01 09:06:56 AM UTC 24 |
Sep 01 09:07:07 AM UTC 24 |
2009241801 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2300105133 |
|
|
Sep 01 09:06:56 AM UTC 24 |
Sep 01 09:07:07 AM UTC 24 |
2107448837 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.3087418737 |
|
|
Sep 01 09:07:04 AM UTC 24 |
Sep 01 09:07:09 AM UTC 24 |
4478382088 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1213741876 |
|
|
Sep 01 09:05:10 AM UTC 24 |
Sep 01 09:07:10 AM UTC 24 |
109365954789 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.2483323449 |
|
|
Sep 01 09:07:17 AM UTC 24 |
Sep 01 09:07:39 AM UTC 24 |
14098100694 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.1398498399 |
|
|
Sep 01 09:07:08 AM UTC 24 |
Sep 01 09:07:12 AM UTC 24 |
2124801801 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2034492464 |
|
|
Sep 01 09:07:02 AM UTC 24 |
Sep 01 09:07:13 AM UTC 24 |
8220182102 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.1355133278 |
|
|
Sep 01 09:05:26 AM UTC 24 |
Sep 01 09:07:15 AM UTC 24 |
75305209192 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.4110364233 |
|
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Sep 01 09:07:10 AM UTC 24 |
Sep 01 09:07:15 AM UTC 24 |
2197885326 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.1467320702 |
|
|
Sep 01 09:07:08 AM UTC 24 |
Sep 01 09:07:15 AM UTC 24 |
2009859911 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.484315375 |
|
|
Sep 01 09:07:01 AM UTC 24 |
Sep 01 09:07:16 AM UTC 24 |
2932175156 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.1580274061 |
|
|
Sep 01 09:07:36 AM UTC 24 |
Sep 01 09:07:41 AM UTC 24 |
2134220186 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.576102866 |
|
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Sep 01 09:05:46 AM UTC 24 |
Sep 01 09:07:16 AM UTC 24 |
112705858523 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.1187487815 |
|
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Sep 01 09:07:10 AM UTC 24 |
Sep 01 09:07:17 AM UTC 24 |
2518321682 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2608668630 |
|
|
Sep 01 09:07:12 AM UTC 24 |
Sep 01 09:07:18 AM UTC 24 |
3130269662 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1205683291 |
|
|
Sep 01 09:07:10 AM UTC 24 |
Sep 01 09:07:18 AM UTC 24 |
2467717421 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.362538754 |
|
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Sep 01 09:04:29 AM UTC 24 |
Sep 01 09:07:18 AM UTC 24 |
50359954077 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2668142551 |
|
|
Sep 01 09:07:03 AM UTC 24 |
Sep 01 09:07:20 AM UTC 24 |
50983418302 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.1740452881 |
|
|
Sep 01 09:07:17 AM UTC 24 |
Sep 01 09:07:21 AM UTC 24 |
2037081299 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.1083641258 |
|
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Sep 01 09:07:17 AM UTC 24 |
Sep 01 09:07:21 AM UTC 24 |
2123019137 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.2061273287 |
|
|
Sep 01 09:07:18 AM UTC 24 |
Sep 01 09:07:21 AM UTC 24 |
2151826649 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.1335073895 |
|
|
Sep 01 09:07:19 AM UTC 24 |
Sep 01 09:07:22 AM UTC 24 |
2603645341 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3534292175 |
|
|
Sep 01 09:07:19 AM UTC 24 |
Sep 01 09:07:23 AM UTC 24 |
2621833170 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3944451326 |
|
|
Sep 01 09:03:50 AM UTC 24 |
Sep 01 09:07:24 AM UTC 24 |
297756844317 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3967930800 |
|
|
Sep 01 09:05:55 AM UTC 24 |
Sep 01 09:07:24 AM UTC 24 |
81727456827 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.42231206 |
|
|
Sep 01 09:07:21 AM UTC 24 |
Sep 01 09:07:26 AM UTC 24 |
3336145033 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2781096762 |
|
|
Sep 01 09:07:07 AM UTC 24 |
Sep 01 09:07:26 AM UTC 24 |
15507807207 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3498176742 |
|
|
Sep 01 09:07:17 AM UTC 24 |
Sep 01 09:07:26 AM UTC 24 |
3860628716 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.4018458818 |
|
|
Sep 01 09:07:10 AM UTC 24 |
Sep 01 09:07:27 AM UTC 24 |
2612725479 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.205548113 |
|
|
Sep 01 09:06:55 AM UTC 24 |
Sep 01 09:07:27 AM UTC 24 |
7035640419 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.1752992670 |
|
|
Sep 01 09:04:14 AM UTC 24 |
Sep 01 09:07:28 AM UTC 24 |
59646180350 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.3326521004 |
|
|
Sep 01 09:04:03 AM UTC 24 |
Sep 01 09:07:28 AM UTC 24 |
84496742817 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.3997882208 |
|
|
Sep 01 09:07:18 AM UTC 24 |
Sep 01 09:07:30 AM UTC 24 |
2457480133 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3163639713 |
|
|
Sep 01 09:07:26 AM UTC 24 |
Sep 01 09:07:30 AM UTC 24 |
2131107810 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2768303530 |
|
|
Sep 01 09:07:26 AM UTC 24 |
Sep 01 09:07:31 AM UTC 24 |
2118846176 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.19440274 |
|
|
Sep 01 09:07:25 AM UTC 24 |
Sep 01 09:07:33 AM UTC 24 |
2013791474 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.1037029894 |
|
|
Sep 01 09:07:26 AM UTC 24 |
Sep 01 09:07:33 AM UTC 24 |
2456375641 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2135701790 |
|
|
Sep 01 09:07:28 AM UTC 24 |
Sep 01 09:07:34 AM UTC 24 |
3389658338 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.3125051555 |
|
|
Sep 01 09:07:16 AM UTC 24 |
Sep 01 09:07:35 AM UTC 24 |
4712506844 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.1425055123 |
|
|
Sep 01 09:07:23 AM UTC 24 |
Sep 01 09:07:35 AM UTC 24 |
4566734148 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2393127358 |
|
|
Sep 01 09:04:57 AM UTC 24 |
Sep 01 09:07:35 AM UTC 24 |
87096367886 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.131804675 |
|
|
Sep 01 09:07:30 AM UTC 24 |
Sep 01 09:07:36 AM UTC 24 |
2681924506 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2581604856 |
|
|
Sep 01 09:07:24 AM UTC 24 |
Sep 01 09:07:38 AM UTC 24 |
32739986248 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.126246715 |
|
|
Sep 01 09:07:12 AM UTC 24 |
Sep 01 09:07:40 AM UTC 24 |
151188908878 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.1660660610 |
|
|
Sep 01 09:07:28 AM UTC 24 |
Sep 01 09:07:41 AM UTC 24 |
2512433146 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.747957026 |
|
|
Sep 01 09:07:36 AM UTC 24 |
Sep 01 09:07:41 AM UTC 24 |
2460207945 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.734531187 |
|
|
Sep 01 09:04:03 AM UTC 24 |
Sep 01 09:07:42 AM UTC 24 |
74139784334 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4117045802 |
|
|
Sep 01 09:07:28 AM UTC 24 |
Sep 01 09:07:42 AM UTC 24 |
2608941802 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1176261681 |
|
|
Sep 01 09:07:28 AM UTC 24 |
Sep 01 09:07:44 AM UTC 24 |
3068880062 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.686661530 |
|
|
Sep 01 09:07:36 AM UTC 24 |
Sep 01 09:07:44 AM UTC 24 |
2012698472 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.1681816108 |
|
|
Sep 01 09:06:22 AM UTC 24 |
Sep 01 09:07:44 AM UTC 24 |
48943564777 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1404224403 |
|
|
Sep 01 09:07:42 AM UTC 24 |
Sep 01 09:07:47 AM UTC 24 |
3062268211 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.3390058000 |
|
|
Sep 01 09:07:45 AM UTC 24 |
Sep 01 09:07:48 AM UTC 24 |
2154932810 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1920837877 |
|
|
Sep 01 09:07:44 AM UTC 24 |
Sep 01 09:07:48 AM UTC 24 |
3085377691 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.2855521760 |
|
|
Sep 01 09:04:48 AM UTC 24 |
Sep 01 09:07:48 AM UTC 24 |
100306104805 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.241423322 |
|
|
Sep 01 09:07:38 AM UTC 24 |
Sep 01 09:07:49 AM UTC 24 |
2512148204 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1931781449 |
|
|
Sep 01 09:07:42 AM UTC 24 |
Sep 01 09:07:50 AM UTC 24 |
3497974905 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.3351237151 |
|
|
Sep 01 09:06:54 AM UTC 24 |
Sep 01 09:07:50 AM UTC 24 |
205667064674 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.3502593354 |
|
|
Sep 01 09:07:38 AM UTC 24 |
Sep 01 09:07:50 AM UTC 24 |
2043858089 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.4082700776 |
|
|
Sep 01 09:07:34 AM UTC 24 |
Sep 01 09:07:51 AM UTC 24 |
22642158221 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.144404006 |
|
|
Sep 01 09:07:48 AM UTC 24 |
Sep 01 09:07:52 AM UTC 24 |
2523260198 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.2563829351 |
|
|
Sep 01 09:07:45 AM UTC 24 |
Sep 01 09:07:52 AM UTC 24 |
2111941066 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2517651902 |
|
|
Sep 01 09:07:41 AM UTC 24 |
Sep 01 09:07:53 AM UTC 24 |
2610131364 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1718148850 |
|
|
Sep 01 09:07:50 AM UTC 24 |
Sep 01 09:07:54 AM UTC 24 |
3895696748 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3703517147 |
|
|
Sep 01 09:07:42 AM UTC 24 |
Sep 01 09:07:55 AM UTC 24 |
5751911997 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3614635492 |
|
|
Sep 01 09:07:50 AM UTC 24 |
Sep 01 09:07:56 AM UTC 24 |
3751086366 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.3812750070 |
|
|
Sep 01 09:07:45 AM UTC 24 |
Sep 01 09:07:56 AM UTC 24 |
2465542641 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.18797156 |
|
|
Sep 01 09:07:54 AM UTC 24 |
Sep 01 09:07:57 AM UTC 24 |
2202369831 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1549221668 |
|
|
Sep 01 09:05:27 AM UTC 24 |
Sep 01 09:07:57 AM UTC 24 |
44783127743 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.1769439537 |
|
|
Sep 01 09:07:47 AM UTC 24 |
Sep 01 09:07:58 AM UTC 24 |
2183800051 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.2515906959 |
|
|
Sep 01 09:06:05 AM UTC 24 |
Sep 01 09:07:58 AM UTC 24 |
69836817399 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3311861433 |
|
|
Sep 01 09:07:54 AM UTC 24 |
Sep 01 09:07:59 AM UTC 24 |
2033291533 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1313836046 |
|
|
Sep 01 09:07:25 AM UTC 24 |
Sep 01 09:07:59 AM UTC 24 |
6472588323 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.2515838290 |
|
|
Sep 01 09:07:36 AM UTC 24 |
Sep 01 09:08:00 AM UTC 24 |
10621831771 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3807862128 |
|
|
Sep 01 09:07:50 AM UTC 24 |
Sep 01 09:08:00 AM UTC 24 |
2612299588 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.122563688 |
|
|
Sep 01 09:07:56 AM UTC 24 |
Sep 01 09:08:01 AM UTC 24 |
2226840667 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3506185846 |
|
|
Sep 01 09:07:51 AM UTC 24 |
Sep 01 09:08:01 AM UTC 24 |
4569936489 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.1972606828 |
|
|
Sep 01 09:07:58 AM UTC 24 |
Sep 01 09:08:02 AM UTC 24 |
2550780390 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3669806549 |
|
|
Sep 01 09:07:58 AM UTC 24 |
Sep 01 09:08:03 AM UTC 24 |
3352121492 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.2528041332 |
|
|
Sep 01 09:07:51 AM UTC 24 |
Sep 01 09:08:04 AM UTC 24 |
3838696851 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3251835053 |
|
|
Sep 01 09:07:59 AM UTC 24 |
Sep 01 09:08:04 AM UTC 24 |
3271741801 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.3448791674 |
|
|
Sep 01 09:05:03 AM UTC 24 |
Sep 01 09:08:07 AM UTC 24 |
70242701769 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.4032545233 |
|
|
Sep 01 09:08:01 AM UTC 24 |
Sep 01 09:08:07 AM UTC 24 |
5617496299 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1410993043 |
|
|
Sep 01 09:07:55 AM UTC 24 |
Sep 01 09:08:08 AM UTC 24 |
2463940356 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2948971406 |
|
|
Sep 01 09:07:53 AM UTC 24 |
Sep 01 09:08:09 AM UTC 24 |
4263955603 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3853278413 |
|
|
Sep 01 09:07:44 AM UTC 24 |
Sep 01 09:08:09 AM UTC 24 |
10425147510 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.2647598205 |
|
|
Sep 01 09:08:04 AM UTC 24 |
Sep 01 09:08:09 AM UTC 24 |
2488980603 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1508995130 |
|
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Sep 01 09:07:58 AM UTC 24 |
Sep 01 09:08:10 AM UTC 24 |
2608195107 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.3315453491 |
|
|
Sep 01 09:08:06 AM UTC 24 |
Sep 01 09:08:10 AM UTC 24 |
2270763727 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.3407353827 |
|
|
Sep 01 09:08:02 AM UTC 24 |
Sep 01 09:08:11 AM UTC 24 |
2110054397 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.1382496620 |
|
|
Sep 01 09:08:01 AM UTC 24 |
Sep 01 09:08:12 AM UTC 24 |
2011918536 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.1316900675 |
|
|
Sep 01 09:08:06 AM UTC 24 |
Sep 01 09:08:13 AM UTC 24 |
2518608820 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.4174484526 |
|
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Sep 01 09:08:08 AM UTC 24 |
Sep 01 09:08:13 AM UTC 24 |
2612585016 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1796176505 |
|
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Sep 01 09:06:54 AM UTC 24 |
Sep 01 09:08:13 AM UTC 24 |
48737673492 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2872332973 |
|
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Sep 01 09:08:00 AM UTC 24 |
Sep 01 09:08:13 AM UTC 24 |
2609598284 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.4283570470 |
|
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Sep 01 09:08:08 AM UTC 24 |
Sep 01 09:08:13 AM UTC 24 |
3506700034 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.297099620 |
|
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Sep 01 09:07:25 AM UTC 24 |
Sep 01 09:08:13 AM UTC 24 |
53251618732 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.4069302333 |
|
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Sep 01 09:08:10 AM UTC 24 |
Sep 01 09:08:15 AM UTC 24 |
2748006844 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.913356799 |
|
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Sep 01 09:08:09 AM UTC 24 |
Sep 01 09:08:16 AM UTC 24 |
3585772558 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1524169695 |
|
|
Sep 01 09:08:12 AM UTC 24 |
Sep 01 09:08:17 AM UTC 24 |
2038049357 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.4238652201 |
|
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Sep 01 09:08:14 AM UTC 24 |
Sep 01 09:08:17 AM UTC 24 |
2059072407 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1259934849 |
|
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Sep 01 09:07:52 AM UTC 24 |
Sep 01 09:08:18 AM UTC 24 |
32401468558 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1595930313 |
|
|
Sep 01 09:08:13 AM UTC 24 |
Sep 01 09:08:18 AM UTC 24 |
2122580702 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1079794424 |
|
|
Sep 01 09:07:53 AM UTC 24 |
Sep 01 09:08:18 AM UTC 24 |
10355684796 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.104146667 |
|
|
Sep 01 09:08:13 AM UTC 24 |
Sep 01 09:08:18 AM UTC 24 |
2477971776 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2126495626 |
|
|
Sep 01 09:08:14 AM UTC 24 |
Sep 01 09:08:19 AM UTC 24 |
2625063457 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.2695015039 |
|
|
Sep 01 09:08:14 AM UTC 24 |
Sep 01 09:08:19 AM UTC 24 |
2525830864 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.678012227 |
|
|
Sep 01 09:05:44 AM UTC 24 |
Sep 01 09:08:19 AM UTC 24 |
50026312187 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.845286559 |
|
|
Sep 01 09:08:16 AM UTC 24 |
Sep 01 09:08:20 AM UTC 24 |
3730119372 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2172601018 |
|
|
Sep 01 09:08:09 AM UTC 24 |
Sep 01 09:08:21 AM UTC 24 |
3166982899 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.2049717901 |
|
|
Sep 01 09:05:54 AM UTC 24 |
Sep 01 09:08:22 AM UTC 24 |
139664261321 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.249763982 |
|
|
Sep 01 09:08:19 AM UTC 24 |
Sep 01 09:08:23 AM UTC 24 |
2063552943 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3162905762 |
|
|
Sep 01 09:08:15 AM UTC 24 |
Sep 01 09:08:24 AM UTC 24 |
2704469775 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2956552442 |
|
|
Sep 01 09:07:16 AM UTC 24 |
Sep 01 09:08:24 AM UTC 24 |
34841807073 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.1898038622 |
|
|
Sep 01 09:08:19 AM UTC 24 |
Sep 01 09:08:31 AM UTC 24 |
2112291844 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.3266783690 |
|
|
Sep 01 09:08:20 AM UTC 24 |
Sep 01 09:08:24 AM UTC 24 |
2483161628 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.229347320 |
|
|
Sep 01 09:07:44 AM UTC 24 |
Sep 01 09:08:25 AM UTC 24 |
106769942715 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1537810499 |
|
|
Sep 01 09:08:25 AM UTC 24 |
Sep 01 09:08:28 AM UTC 24 |
5883576923 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.482266866 |
|
|
Sep 01 09:08:17 AM UTC 24 |
Sep 01 09:08:28 AM UTC 24 |
3024766964 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.489310586 |
|
|
Sep 01 09:08:23 AM UTC 24 |
Sep 01 09:08:29 AM UTC 24 |
3011728557 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.1767154232 |
|
|
Sep 01 09:08:21 AM UTC 24 |
Sep 01 09:08:29 AM UTC 24 |
2512107111 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.3934762314 |
|
|
Sep 01 09:08:18 AM UTC 24 |
Sep 01 09:08:29 AM UTC 24 |
3109639859 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.3996488821 |
|
|
Sep 01 09:08:21 AM UTC 24 |
Sep 01 09:08:30 AM UTC 24 |
2049757334 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.635539770 |
|
|
Sep 01 09:08:23 AM UTC 24 |
Sep 01 09:08:31 AM UTC 24 |
3780772078 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3077973887 |
|
|
Sep 01 09:07:20 AM UTC 24 |
Sep 01 09:08:32 AM UTC 24 |
196949440224 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.1756844636 |
|
|
Sep 01 09:08:30 AM UTC 24 |
Sep 01 09:08:32 AM UTC 24 |
2116857522 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.809925804 |
|
|
Sep 01 09:08:19 AM UTC 24 |
Sep 01 09:08:34 AM UTC 24 |
12202014674 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.2002756370 |
|
|
Sep 01 09:08:30 AM UTC 24 |
Sep 01 09:08:35 AM UTC 24 |
2478949920 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.4072769414 |
|
|
Sep 01 09:08:22 AM UTC 24 |
Sep 01 09:08:35 AM UTC 24 |
2610046072 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3246200276 |
|
|
Sep 01 09:08:33 AM UTC 24 |
Sep 01 09:08:39 AM UTC 24 |
4102923346 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.432385060 |
|
|
Sep 01 09:08:32 AM UTC 24 |
Sep 01 09:08:39 AM UTC 24 |
2512415060 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.487034169 |
|
|
Sep 01 09:08:31 AM UTC 24 |
Sep 01 09:08:40 AM UTC 24 |
2244252353 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.3876899314 |
|
|
Sep 01 09:08:30 AM UTC 24 |
Sep 01 09:08:41 AM UTC 24 |
2113312049 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.999177883 |
|
|
Sep 01 09:08:11 AM UTC 24 |
Sep 01 09:08:41 AM UTC 24 |
6434917939 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2513857178 |
|
|
Sep 01 09:05:42 AM UTC 24 |
Sep 01 09:08:41 AM UTC 24 |
47790566825 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2714614619 |
|
|
Sep 01 09:08:35 AM UTC 24 |
Sep 01 09:08:42 AM UTC 24 |
8022920987 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1329705667 |
|
|
Sep 01 09:05:11 AM UTC 24 |
Sep 01 09:08:44 AM UTC 24 |
78063064461 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2401802202 |
|
|
Sep 01 09:08:35 AM UTC 24 |
Sep 01 09:08:44 AM UTC 24 |
3610823539 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.16986542 |
|
|
Sep 01 09:06:32 AM UTC 24 |
Sep 01 09:08:45 AM UTC 24 |
170673398897 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.223826597 |
|
|
Sep 01 09:08:42 AM UTC 24 |
Sep 01 09:08:45 AM UTC 24 |
2049424464 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.2662817737 |
|
|
Sep 01 09:08:42 AM UTC 24 |
Sep 01 09:08:47 AM UTC 24 |
2474721843 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2574573522 |
|
|
Sep 01 09:08:32 AM UTC 24 |
Sep 01 09:08:47 AM UTC 24 |
2612330412 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.1587769916 |
|
|
Sep 01 09:08:01 AM UTC 24 |
Sep 01 09:08:48 AM UTC 24 |
12497749319 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.3610561624 |
|
|
Sep 01 09:07:33 AM UTC 24 |
Sep 01 09:08:50 AM UTC 24 |
96300980513 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1568014627 |
|
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Sep 01 09:07:34 AM UTC 24 |
Sep 01 09:08:50 AM UTC 24 |
21833566516 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.44858378 |
|
|
Sep 01 09:08:42 AM UTC 24 |
Sep 01 09:08:50 AM UTC 24 |
2110871947 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.487670214 |
|
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Sep 01 09:08:28 AM UTC 24 |
Sep 01 09:08:50 AM UTC 24 |
4469618005 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.2074900053 |
|
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Sep 01 09:08:44 AM UTC 24 |
Sep 01 09:08:51 AM UTC 24 |
2516623440 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2001550068 |
|
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Sep 01 09:08:46 AM UTC 24 |
Sep 01 09:08:52 AM UTC 24 |
3516480421 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.275346494 |
|
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Sep 01 09:08:45 AM UTC 24 |
Sep 01 09:08:52 AM UTC 24 |
2620828548 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2718919149 |
|
|
Sep 01 09:08:11 AM UTC 24 |
Sep 01 09:08:52 AM UTC 24 |
38327411183 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.1329433102 |
|
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Sep 01 09:08:43 AM UTC 24 |
Sep 01 09:08:54 AM UTC 24 |
2158203273 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.1703599287 |
|
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Sep 01 09:08:52 AM UTC 24 |
Sep 01 09:08:55 AM UTC 24 |
2037335721 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.325536409 |
|
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Sep 01 09:08:53 AM UTC 24 |
Sep 01 09:08:57 AM UTC 24 |
2140428296 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.1537315720 |
|
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Sep 01 09:08:49 AM UTC 24 |
Sep 01 09:08:57 AM UTC 24 |
5675393786 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.320752235 |
|
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Sep 01 09:07:07 AM UTC 24 |
Sep 01 09:09:00 AM UTC 24 |
145230200498 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3786282678 |
|
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Sep 01 09:08:40 AM UTC 24 |
Sep 01 09:09:01 AM UTC 24 |
45622535554 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2614213246 |
|
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Sep 01 09:08:46 AM UTC 24 |
Sep 01 09:09:01 AM UTC 24 |
4469156774 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.930054852 |
|
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Sep 01 09:08:53 AM UTC 24 |
Sep 01 09:09:03 AM UTC 24 |
2468231296 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1569807815 |
|
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Sep 01 09:08:58 AM UTC 24 |
Sep 01 09:09:03 AM UTC 24 |
8391747726 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.94265347 |
|
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Sep 01 09:08:30 AM UTC 24 |
Sep 01 09:09:03 AM UTC 24 |
2871793844890 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.3226057742 |
|
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Sep 01 09:09:14 AM UTC 24 |
Sep 01 09:09:18 AM UTC 24 |
2451054847 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.375558762 |
|
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Sep 01 09:06:07 AM UTC 24 |
Sep 01 09:09:04 AM UTC 24 |
50556018202 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.4222820098 |
|
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Sep 01 09:08:53 AM UTC 24 |
Sep 01 09:09:05 AM UTC 24 |
2200025651 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.1503087381 |
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Sep 01 09:09:01 AM UTC 24 |
Sep 01 09:09:05 AM UTC 24 |
2506824811 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3803463710 |
|
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Sep 01 09:08:52 AM UTC 24 |
Sep 01 09:09:05 AM UTC 24 |
9001894601 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.216908716 |
|
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Sep 01 09:08:55 AM UTC 24 |
Sep 01 09:09:06 AM UTC 24 |
2613044841 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.1252568944 |
|
|
Sep 01 09:04:33 AM UTC 24 |
Sep 01 09:09:07 AM UTC 24 |
145868982626 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.3591349494 |
|
|
Sep 01 09:08:53 AM UTC 24 |
Sep 01 09:09:07 AM UTC 24 |
2513131103 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.3046122241 |
|
|
Sep 01 09:09:04 AM UTC 24 |
Sep 01 09:09:08 AM UTC 24 |
2035594963 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.142994636 |
|
|
Sep 01 09:07:04 AM UTC 24 |
Sep 01 09:09:08 AM UTC 24 |
139627607243 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.2860613137 |
|
|
Sep 01 09:09:05 AM UTC 24 |
Sep 01 09:09:10 AM UTC 24 |
2476824699 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.4241936347 |
|
|
Sep 01 09:08:10 AM UTC 24 |
Sep 01 09:09:11 AM UTC 24 |
79622507992 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.2249945298 |
|
|
Sep 01 09:09:06 AM UTC 24 |
Sep 01 09:09:11 AM UTC 24 |
2528703395 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2702036518 |
|
|
Sep 01 09:09:06 AM UTC 24 |
Sep 01 09:09:12 AM UTC 24 |
2251515895 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1958368219 |
|
|
Sep 01 09:09:07 AM UTC 24 |
Sep 01 09:09:12 AM UTC 24 |
2730562127 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1995862162 |
|
|
Sep 01 09:09:07 AM UTC 24 |
Sep 01 09:09:13 AM UTC 24 |
3273321668 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2270536498 |
|
|
Sep 01 09:09:06 AM UTC 24 |
Sep 01 09:09:13 AM UTC 24 |
2621941256 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.163674227 |
|
|
Sep 01 09:08:56 AM UTC 24 |
Sep 01 09:09:14 AM UTC 24 |
3038050155 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.2059417695 |
|
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Sep 01 09:09:09 AM UTC 24 |
Sep 01 09:09:14 AM UTC 24 |
5280493019 ps |