| T400 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.4071149631 |
|
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Sep 01 09:08:40 AM UTC 24 |
Sep 01 09:09:15 AM UTC 24 |
114949301481 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2829400981 |
|
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Sep 01 09:09:05 AM UTC 24 |
Sep 01 09:09:16 AM UTC 24 |
2112999461 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.3117966420 |
|
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Sep 01 09:09:13 AM UTC 24 |
Sep 01 09:09:16 AM UTC 24 |
2161873614 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.1198507089 |
|
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Sep 01 09:09:13 AM UTC 24 |
Sep 01 09:09:16 AM UTC 24 |
2063009572 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.4252689657 |
|
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Sep 01 09:06:34 AM UTC 24 |
Sep 01 09:09:16 AM UTC 24 |
49045888075 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3415312678 |
|
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Sep 01 09:08:01 AM UTC 24 |
Sep 01 09:09:17 AM UTC 24 |
37878462431 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2183329948 |
|
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Sep 01 09:07:42 AM UTC 24 |
Sep 01 09:09:19 AM UTC 24 |
134419187220 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2131598528 |
|
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Sep 01 09:08:57 AM UTC 24 |
Sep 01 09:09:19 AM UTC 24 |
32768313709 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3108300857 |
|
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Sep 01 09:04:48 AM UTC 24 |
Sep 01 09:09:20 AM UTC 24 |
74859870424 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.691720037 |
|
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Sep 01 09:09:07 AM UTC 24 |
Sep 01 09:09:20 AM UTC 24 |
3361268190 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.2580700834 |
|
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Sep 01 09:08:25 AM UTC 24 |
Sep 01 09:09:21 AM UTC 24 |
16490685094 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2529663685 |
|
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Sep 01 09:09:12 AM UTC 24 |
Sep 01 09:09:21 AM UTC 24 |
19249660879 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.18374639 |
|
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Sep 01 09:09:17 AM UTC 24 |
Sep 01 09:09:22 AM UTC 24 |
6025464263 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3195308670 |
|
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Sep 01 09:09:17 AM UTC 24 |
Sep 01 09:09:23 AM UTC 24 |
3692906667 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.1290763777 |
|
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Sep 01 09:09:49 AM UTC 24 |
Sep 01 09:09:54 AM UTC 24 |
2146782891 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.368884206 |
|
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Sep 01 09:09:18 AM UTC 24 |
Sep 01 09:09:23 AM UTC 24 |
3162589573 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.367568644 |
|
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Sep 01 09:09:15 AM UTC 24 |
Sep 01 09:09:23 AM UTC 24 |
2521639430 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3693184932 |
|
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Sep 01 09:09:15 AM UTC 24 |
Sep 01 09:09:24 AM UTC 24 |
2617397489 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.141583470 |
|
|
Sep 01 09:08:52 AM UTC 24 |
Sep 01 09:09:24 AM UTC 24 |
9647501876 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.439776675 |
|
|
Sep 01 09:09:21 AM UTC 24 |
Sep 01 09:09:24 AM UTC 24 |
2515299518 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.2383315149 |
|
|
Sep 01 09:08:42 AM UTC 24 |
Sep 01 09:09:25 AM UTC 24 |
13389160323 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.802659576 |
|
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Sep 01 09:06:06 AM UTC 24 |
Sep 01 09:09:25 AM UTC 24 |
54221937503 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.3551804209 |
|
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Sep 01 09:09:21 AM UTC 24 |
Sep 01 09:09:25 AM UTC 24 |
2130225912 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2406226416 |
|
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Sep 01 09:09:22 AM UTC 24 |
Sep 01 09:09:26 AM UTC 24 |
2546511255 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.1833429567 |
|
|
Sep 01 09:09:14 AM UTC 24 |
Sep 01 09:09:26 AM UTC 24 |
2255570900 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.3941008443 |
|
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Sep 01 09:06:46 AM UTC 24 |
Sep 01 09:09:27 AM UTC 24 |
548966945096 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1505196378 |
|
|
Sep 01 09:04:09 AM UTC 24 |
Sep 01 09:09:28 AM UTC 24 |
110326885164 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2987114887 |
|
|
Sep 01 09:09:16 AM UTC 24 |
Sep 01 09:09:28 AM UTC 24 |
4713737033 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3715295501 |
|
|
Sep 01 09:09:23 AM UTC 24 |
Sep 01 09:09:28 AM UTC 24 |
2632550163 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.2777936022 |
|
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Sep 01 09:09:22 AM UTC 24 |
Sep 01 09:09:30 AM UTC 24 |
2147975632 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.662523333 |
|
|
Sep 01 09:07:23 AM UTC 24 |
Sep 01 09:09:30 AM UTC 24 |
151319623808 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.2875215820 |
|
|
Sep 01 09:09:28 AM UTC 24 |
Sep 01 09:09:30 AM UTC 24 |
2657396318 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3172618928 |
|
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Sep 01 09:09:24 AM UTC 24 |
Sep 01 09:09:30 AM UTC 24 |
3495700426 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.2544250948 |
|
|
Sep 01 09:09:26 AM UTC 24 |
Sep 01 09:09:31 AM UTC 24 |
2028735764 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.233930391 |
|
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Sep 01 09:09:20 AM UTC 24 |
Sep 01 09:09:31 AM UTC 24 |
7796129785 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2898292950 |
|
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Sep 01 09:09:04 AM UTC 24 |
Sep 01 09:09:32 AM UTC 24 |
4785372579 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2693783230 |
|
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Sep 01 09:09:20 AM UTC 24 |
Sep 01 09:09:32 AM UTC 24 |
2011654747 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3235105799 |
|
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Sep 01 09:09:24 AM UTC 24 |
Sep 01 09:09:33 AM UTC 24 |
7713823138 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.3702688197 |
|
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Sep 01 09:09:26 AM UTC 24 |
Sep 01 09:09:34 AM UTC 24 |
3712237030 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2212000731 |
|
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Sep 01 09:08:50 AM UTC 24 |
Sep 01 09:09:35 AM UTC 24 |
49915376626 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3564574299 |
|
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Sep 01 09:04:55 AM UTC 24 |
Sep 01 09:09:35 AM UTC 24 |
178541869497 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3155124734 |
|
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Sep 01 09:09:30 AM UTC 24 |
Sep 01 09:09:36 AM UTC 24 |
3471165325 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1016517141 |
|
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Sep 01 09:09:24 AM UTC 24 |
Sep 01 09:09:36 AM UTC 24 |
3846124626 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.3327030241 |
|
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Sep 01 09:09:28 AM UTC 24 |
Sep 01 09:09:36 AM UTC 24 |
2162016481 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2280327001 |
|
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Sep 01 09:09:29 AM UTC 24 |
Sep 01 09:09:37 AM UTC 24 |
4510889537 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.3774933092 |
|
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Sep 01 09:09:33 AM UTC 24 |
Sep 01 09:09:37 AM UTC 24 |
2035486890 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2164182119 |
|
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Sep 01 09:07:59 AM UTC 24 |
Sep 01 09:09:37 AM UTC 24 |
2336363356391 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.3466657168 |
|
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Sep 01 09:09:27 AM UTC 24 |
Sep 01 09:09:38 AM UTC 24 |
2111901392 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.1801901844 |
|
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Sep 01 09:09:27 AM UTC 24 |
Sep 01 09:09:38 AM UTC 24 |
2443922658 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.112057484 |
|
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Sep 01 09:09:26 AM UTC 24 |
Sep 01 09:09:38 AM UTC 24 |
12011601488 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1858140829 |
|
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Sep 01 09:04:23 AM UTC 24 |
Sep 01 09:09:39 AM UTC 24 |
98695455988 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2426567564 |
|
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Sep 01 09:03:51 AM UTC 24 |
Sep 01 09:09:40 AM UTC 24 |
130566321599 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.2725386049 |
|
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Sep 01 09:09:35 AM UTC 24 |
Sep 01 09:09:41 AM UTC 24 |
2481988946 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.933911972 |
|
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Sep 01 09:09:29 AM UTC 24 |
Sep 01 09:09:41 AM UTC 24 |
2611768927 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.3141329264 |
|
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Sep 01 09:09:36 AM UTC 24 |
Sep 01 09:09:42 AM UTC 24 |
2530836537 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1557842870 |
|
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Sep 01 09:09:35 AM UTC 24 |
Sep 01 09:09:42 AM UTC 24 |
2102583555 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2465218692 |
|
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Sep 01 09:09:02 AM UTC 24 |
Sep 01 09:09:43 AM UTC 24 |
53560075377 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2146774532 |
|
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Sep 01 09:09:36 AM UTC 24 |
Sep 01 09:09:43 AM UTC 24 |
2617933726 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3691546802 |
|
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Sep 01 09:09:36 AM UTC 24 |
Sep 01 09:09:43 AM UTC 24 |
3714698988 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.668338038 |
|
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Sep 01 09:09:26 AM UTC 24 |
Sep 01 09:09:44 AM UTC 24 |
450372833889 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.562504456 |
|
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Sep 01 09:09:34 AM UTC 24 |
Sep 01 09:09:45 AM UTC 24 |
2108504851 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.875767893 |
|
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Sep 01 09:09:42 AM UTC 24 |
Sep 01 09:09:46 AM UTC 24 |
2035042836 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3299174636 |
|
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Sep 01 09:09:38 AM UTC 24 |
Sep 01 09:09:46 AM UTC 24 |
5876597654 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.2395602566 |
|
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Sep 01 09:09:40 AM UTC 24 |
Sep 01 09:09:46 AM UTC 24 |
2016357397 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.3909265505 |
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Sep 01 09:09:43 AM UTC 24 |
Sep 01 09:09:47 AM UTC 24 |
2553816810 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.238038947 |
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Sep 01 09:09:32 AM UTC 24 |
Sep 01 09:09:48 AM UTC 24 |
3246747591 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.4046353996 |
|
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Sep 01 09:09:36 AM UTC 24 |
Sep 01 09:09:48 AM UTC 24 |
2605050851 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1246541870 |
|
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Sep 01 09:09:45 AM UTC 24 |
Sep 01 09:09:49 AM UTC 24 |
10449024828 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1230807139 |
|
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Sep 01 09:09:43 AM UTC 24 |
Sep 01 09:09:49 AM UTC 24 |
3521845776 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.190119463 |
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Sep 01 09:09:38 AM UTC 24 |
Sep 01 09:09:49 AM UTC 24 |
2735101464 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.3498758025 |
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Sep 01 09:09:41 AM UTC 24 |
Sep 01 09:09:52 AM UTC 24 |
2107802595 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.257666837 |
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Sep 01 09:09:48 AM UTC 24 |
Sep 01 09:09:52 AM UTC 24 |
2126837469 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1742049597 |
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Sep 01 09:09:46 AM UTC 24 |
Sep 01 09:09:53 AM UTC 24 |
3871985172 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.1923533386 |
|
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Sep 01 09:09:49 AM UTC 24 |
Sep 01 09:09:53 AM UTC 24 |
2483420614 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.2917113337 |
|
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Sep 01 09:09:42 AM UTC 24 |
Sep 01 09:09:53 AM UTC 24 |
2458410642 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3328730293 |
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Sep 01 09:09:33 AM UTC 24 |
Sep 01 09:09:53 AM UTC 24 |
21830212646 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.3035206161 |
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Sep 01 09:09:47 AM UTC 24 |
Sep 01 09:09:53 AM UTC 24 |
2019577758 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.2735995764 |
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Sep 01 09:09:49 AM UTC 24 |
Sep 01 09:09:53 AM UTC 24 |
2542922014 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1800712511 |
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Sep 01 09:09:49 AM UTC 24 |
Sep 01 09:09:54 AM UTC 24 |
2629896571 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.963047185 |
|
|
Sep 01 09:09:52 AM UTC 24 |
Sep 01 09:09:55 AM UTC 24 |
6510275430 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.1965093279 |
|
|
Sep 01 09:09:47 AM UTC 24 |
Sep 01 09:09:56 AM UTC 24 |
11628313808 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.2646501328 |
|
|
Sep 01 09:09:53 AM UTC 24 |
Sep 01 09:09:57 AM UTC 24 |
3324100117 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1709018324 |
|
|
Sep 01 09:09:43 AM UTC 24 |
Sep 01 09:09:58 AM UTC 24 |
2612890911 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.2243096875 |
|
|
Sep 01 09:09:54 AM UTC 24 |
Sep 01 09:09:58 AM UTC 24 |
2136965100 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1800246006 |
|
|
Sep 01 09:09:49 AM UTC 24 |
Sep 01 09:09:59 AM UTC 24 |
2613727895 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2380404851 |
|
|
Sep 01 09:09:47 AM UTC 24 |
Sep 01 09:09:59 AM UTC 24 |
4164780156 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.1031288469 |
|
|
Sep 01 09:09:54 AM UTC 24 |
Sep 01 09:10:02 AM UTC 24 |
2477113125 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2788519834 |
|
|
Sep 01 09:09:43 AM UTC 24 |
Sep 01 09:10:02 AM UTC 24 |
4474301093 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.3289592848 |
|
|
Sep 01 09:08:35 AM UTC 24 |
Sep 01 09:10:03 AM UTC 24 |
138169742931 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.153730231 |
|
|
Sep 01 09:09:55 AM UTC 24 |
Sep 01 09:10:03 AM UTC 24 |
2519803441 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1909792123 |
|
|
Sep 01 09:09:56 AM UTC 24 |
Sep 01 09:10:04 AM UTC 24 |
3017288542 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.4107063208 |
|
|
Sep 01 09:10:00 AM UTC 24 |
Sep 01 09:10:05 AM UTC 24 |
4446510874 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.37200993 |
|
|
Sep 01 09:09:54 AM UTC 24 |
Sep 01 09:10:05 AM UTC 24 |
2013661562 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.444313862 |
|
|
Sep 01 09:09:55 AM UTC 24 |
Sep 01 09:10:07 AM UTC 24 |
2227020057 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3826930936 |
|
|
Sep 01 09:09:33 AM UTC 24 |
Sep 01 09:10:07 AM UTC 24 |
17762811922 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.496289581 |
|
|
Sep 01 09:09:59 AM UTC 24 |
Sep 01 09:10:07 AM UTC 24 |
6472317599 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.210014508 |
|
|
Sep 01 09:09:39 AM UTC 24 |
Sep 01 09:10:08 AM UTC 24 |
5512089441 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.2853861625 |
|
|
Sep 01 09:06:43 AM UTC 24 |
Sep 01 09:10:08 AM UTC 24 |
136609443698 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.422214908 |
|
|
Sep 01 09:09:54 AM UTC 24 |
Sep 01 09:10:08 AM UTC 24 |
5333534056 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.8417148 |
|
|
Sep 01 09:09:01 AM UTC 24 |
Sep 01 09:10:10 AM UTC 24 |
35369116174 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3354552878 |
|
|
Sep 01 09:09:56 AM UTC 24 |
Sep 01 09:10:10 AM UTC 24 |
2611541662 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2250023404 |
|
|
Sep 01 09:10:04 AM UTC 24 |
Sep 01 09:10:11 AM UTC 24 |
2016887473 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.2560233527 |
|
|
Sep 01 09:10:04 AM UTC 24 |
Sep 01 09:10:11 AM UTC 24 |
2123419775 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1597484643 |
|
|
Sep 01 09:08:47 AM UTC 24 |
Sep 01 09:10:11 AM UTC 24 |
2158646970314 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3536836667 |
|
|
Sep 01 09:09:57 AM UTC 24 |
Sep 01 09:10:11 AM UTC 24 |
2920330411 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.2448310288 |
|
|
Sep 01 09:09:39 AM UTC 24 |
Sep 01 09:10:11 AM UTC 24 |
14035232369 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.1054981654 |
|
|
Sep 01 09:09:24 AM UTC 24 |
Sep 01 09:10:12 AM UTC 24 |
124426406635 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.971165000 |
|
|
Sep 01 09:10:07 AM UTC 24 |
Sep 01 09:10:12 AM UTC 24 |
2703711503 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1349444406 |
|
|
Sep 01 09:10:07 AM UTC 24 |
Sep 01 09:10:12 AM UTC 24 |
2626531036 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3085233006 |
|
|
Sep 01 09:05:03 AM UTC 24 |
Sep 01 09:10:13 AM UTC 24 |
3873409797280 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.1240733797 |
|
|
Sep 01 09:10:06 AM UTC 24 |
Sep 01 09:10:13 AM UTC 24 |
2143856857 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.664805563 |
|
|
Sep 01 09:09:12 AM UTC 24 |
Sep 01 09:10:14 AM UTC 24 |
153533408250 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3304267903 |
|
|
Sep 01 09:08:33 AM UTC 24 |
Sep 01 09:10:14 AM UTC 24 |
123104978586 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.2487130796 |
|
|
Sep 01 09:10:05 AM UTC 24 |
Sep 01 09:10:14 AM UTC 24 |
2448415345 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4179916129 |
|
|
Sep 01 09:10:28 AM UTC 24 |
Sep 01 09:10:33 AM UTC 24 |
3403618647 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.393885972 |
|
|
Sep 01 09:10:09 AM UTC 24 |
Sep 01 09:10:15 AM UTC 24 |
5896498385 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.15838042 |
|
|
Sep 01 09:10:12 AM UTC 24 |
Sep 01 09:10:15 AM UTC 24 |
2067636330 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.922983145 |
|
|
Sep 01 09:10:12 AM UTC 24 |
Sep 01 09:10:16 AM UTC 24 |
2074515522 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2070064000 |
|
|
Sep 01 09:10:09 AM UTC 24 |
Sep 01 09:10:16 AM UTC 24 |
3556802365 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2948822748 |
|
|
Sep 01 09:10:14 AM UTC 24 |
Sep 01 09:10:17 AM UTC 24 |
3137868373 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2304737115 |
|
|
Sep 01 09:10:14 AM UTC 24 |
Sep 01 09:10:17 AM UTC 24 |
2885295604 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.2058476180 |
|
|
Sep 01 09:10:12 AM UTC 24 |
Sep 01 09:10:17 AM UTC 24 |
2474502366 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.513369083 |
|
|
Sep 01 09:09:54 AM UTC 24 |
Sep 01 09:10:17 AM UTC 24 |
126520317536 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2167236013 |
|
|
Sep 01 09:10:13 AM UTC 24 |
Sep 01 09:10:19 AM UTC 24 |
2627640122 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.4188019247 |
|
|
Sep 01 09:10:06 AM UTC 24 |
Sep 01 09:10:20 AM UTC 24 |
2512213434 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1811465806 |
|
|
Sep 01 09:10:03 AM UTC 24 |
Sep 01 09:10:22 AM UTC 24 |
5399797454 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3035447231 |
|
|
Sep 01 09:10:17 AM UTC 24 |
Sep 01 09:10:22 AM UTC 24 |
2480148981 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.672478287 |
|
|
Sep 01 09:10:18 AM UTC 24 |
Sep 01 09:10:22 AM UTC 24 |
2119061354 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2668340917 |
|
|
Sep 01 09:05:37 AM UTC 24 |
Sep 01 09:10:22 AM UTC 24 |
333306565225 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.169098410 |
|
|
Sep 01 09:10:18 AM UTC 24 |
Sep 01 09:10:22 AM UTC 24 |
2623944375 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1472090846 |
|
|
Sep 01 09:10:09 AM UTC 24 |
Sep 01 09:10:23 AM UTC 24 |
5852650210 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.4036598903 |
|
|
Sep 01 09:10:12 AM UTC 24 |
Sep 01 09:10:23 AM UTC 24 |
2111974453 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.59467185 |
|
|
Sep 01 09:10:16 AM UTC 24 |
Sep 01 09:10:24 AM UTC 24 |
13325826056 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.3225528020 |
|
|
Sep 01 09:10:17 AM UTC 24 |
Sep 01 09:10:24 AM UTC 24 |
2017191485 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3145684875 |
|
|
Sep 01 09:10:17 AM UTC 24 |
Sep 01 09:10:24 AM UTC 24 |
2112603490 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.17737045 |
|
|
Sep 01 09:09:11 AM UTC 24 |
Sep 01 09:10:25 AM UTC 24 |
100270566714 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.4159536809 |
|
|
Sep 01 09:10:03 AM UTC 24 |
Sep 01 09:10:25 AM UTC 24 |
15378892419 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.2314724283 |
|
|
Sep 01 09:10:24 AM UTC 24 |
Sep 01 09:10:27 AM UTC 24 |
2065056793 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.4141215285 |
|
|
Sep 01 09:10:23 AM UTC 24 |
Sep 01 09:10:27 AM UTC 24 |
3651332686 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.397250551 |
|
|
Sep 01 09:10:13 AM UTC 24 |
Sep 01 09:10:27 AM UTC 24 |
2508606448 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.462451338 |
|
|
Sep 01 09:10:18 AM UTC 24 |
Sep 01 09:10:27 AM UTC 24 |
2514394542 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.1887028607 |
|
|
Sep 01 09:10:15 AM UTC 24 |
Sep 01 09:10:28 AM UTC 24 |
3269421487 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3016058975 |
|
|
Sep 01 09:08:26 AM UTC 24 |
Sep 01 09:10:29 AM UTC 24 |
120900040157 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.4093522197 |
|
|
Sep 01 09:10:25 AM UTC 24 |
Sep 01 09:10:29 AM UTC 24 |
2653827928 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.279061643 |
|
|
Sep 01 09:10:25 AM UTC 24 |
Sep 01 09:10:30 AM UTC 24 |
2136155394 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.882413897 |
|
|
Sep 01 09:10:25 AM UTC 24 |
Sep 01 09:10:30 AM UTC 24 |
2462049466 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2884394304 |
|
|
Sep 01 09:10:15 AM UTC 24 |
Sep 01 09:10:30 AM UTC 24 |
10941547883 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2767983960 |
|
|
Sep 01 09:10:22 AM UTC 24 |
Sep 01 09:10:31 AM UTC 24 |
3893281806 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.1715061660 |
|
|
Sep 01 09:10:25 AM UTC 24 |
Sep 01 09:10:31 AM UTC 24 |
2059991311 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.713923528 |
|
|
Sep 01 09:10:27 AM UTC 24 |
Sep 01 09:10:33 AM UTC 24 |
3212271764 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.727622902 |
|
|
Sep 01 09:10:25 AM UTC 24 |
Sep 01 09:10:33 AM UTC 24 |
2515186812 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.792811487 |
|
|
Sep 01 09:10:28 AM UTC 24 |
Sep 01 09:10:33 AM UTC 24 |
8143488204 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1752328008 |
|
|
Sep 01 09:10:11 AM UTC 24 |
Sep 01 09:10:34 AM UTC 24 |
9382820611 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.605208208 |
|
|
Sep 01 09:10:30 AM UTC 24 |
Sep 01 09:10:34 AM UTC 24 |
5160555569 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.2241465297 |
|
|
Sep 01 09:10:31 AM UTC 24 |
Sep 01 09:10:34 AM UTC 24 |
2046615538 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1621087739 |
|
|
Sep 01 09:10:23 AM UTC 24 |
Sep 01 09:10:34 AM UTC 24 |
3585919782 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.1553521961 |
|
|
Sep 01 09:10:31 AM UTC 24 |
Sep 01 09:10:36 AM UTC 24 |
16101801913 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3029138256 |
|
|
Sep 01 09:09:31 AM UTC 24 |
Sep 01 09:10:36 AM UTC 24 |
1443439789449 ps |
| T249 |
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Sep 01 09:10:32 AM UTC 24 |
Sep 01 09:10:42 AM UTC 24 |
30009362084 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3757175680 |
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Sep 01 09:10:16 AM UTC 24 |
Sep 01 09:10:43 AM UTC 24 |
16674726206 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.3633521947 |
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Sep 01 09:09:45 AM UTC 24 |
Sep 01 09:10:43 AM UTC 24 |
74595343632 ps |
| T369 |
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Sep 01 09:09:47 AM UTC 24 |
Sep 01 09:10:44 AM UTC 24 |
86024531000 ps |
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/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.3957286729 |
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Sep 01 09:09:04 AM UTC 24 |
Sep 01 09:10:45 AM UTC 24 |
70978886167 ps |
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Sep 01 09:07:51 AM UTC 24 |
Sep 01 09:10:45 AM UTC 24 |
56950949021 ps |
| T762 |
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Sep 01 09:10:31 AM UTC 24 |
Sep 01 09:10:51 AM UTC 24 |
18240548935 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3599222814 |
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Sep 01 09:10:24 AM UTC 24 |
Sep 01 09:10:51 AM UTC 24 |
4369874171 ps |
| T250 |
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Sep 01 09:10:23 AM UTC 24 |
Sep 01 09:10:53 AM UTC 24 |
24116391919 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.1441922884 |
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Sep 01 09:10:24 AM UTC 24 |
Sep 01 09:10:54 AM UTC 24 |
7727574095 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.1918446855 |
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Sep 01 09:10:09 AM UTC 24 |
Sep 01 09:11:02 AM UTC 24 |
76240912244 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.1056052680 |
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Sep 01 09:08:25 AM UTC 24 |
Sep 01 09:11:03 AM UTC 24 |
169674999406 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.120490835 |
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Sep 01 09:09:32 AM UTC 24 |
Sep 01 09:11:04 AM UTC 24 |
33780104990 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.508017764 |
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Sep 01 09:10:31 AM UTC 24 |
Sep 01 09:11:04 AM UTC 24 |
24608616756 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3259140351 |
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Sep 01 09:10:33 AM UTC 24 |
Sep 01 09:11:07 AM UTC 24 |
31550000216 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.1161421430 |
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Sep 01 09:10:15 AM UTC 24 |
Sep 01 09:11:08 AM UTC 24 |
43083743656 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.572779333 |
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Sep 01 09:04:39 AM UTC 24 |
Sep 01 09:11:08 AM UTC 24 |
130243200117 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.2353706007 |
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Sep 01 09:09:38 AM UTC 24 |
Sep 01 09:11:10 AM UTC 24 |
111121162530 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3332700358 |
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Sep 01 09:10:11 AM UTC 24 |
Sep 01 09:11:11 AM UTC 24 |
103493809576 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2391832864 |
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Sep 01 09:11:34 AM UTC 24 |
Sep 01 09:13:22 AM UTC 24 |
112922984711 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2087369873 |
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Sep 01 09:09:39 AM UTC 24 |
Sep 01 09:11:17 AM UTC 24 |
25833809062 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.756306368 |
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Sep 01 09:08:11 AM UTC 24 |
Sep 01 09:13:09 AM UTC 24 |
97043153261 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.4200392607 |
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Sep 01 09:11:40 AM UTC 24 |
Sep 01 09:13:10 AM UTC 24 |
81162699406 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.925761522 |
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Sep 01 09:09:20 AM UTC 24 |
Sep 01 09:11:19 AM UTC 24 |
107869769547 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.598892280 |
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Sep 01 09:08:17 AM UTC 24 |
Sep 01 09:11:22 AM UTC 24 |
56209140055 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1384420526 |
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Sep 01 09:08:18 AM UTC 24 |
Sep 01 09:11:27 AM UTC 24 |
57239228293 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.3607294567 |
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Sep 01 09:10:11 AM UTC 24 |
Sep 01 09:11:28 AM UTC 24 |
172690933951 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2380285454 |
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Sep 01 09:10:36 AM UTC 24 |
Sep 01 09:11:29 AM UTC 24 |
30917041997 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1606718265 |
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Sep 01 09:11:04 AM UTC 24 |
Sep 01 09:11:29 AM UTC 24 |
28465797589 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2586362023 |
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Sep 01 09:10:34 AM UTC 24 |
Sep 01 09:11:31 AM UTC 24 |
32366970798 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.445896340 |
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Sep 01 09:10:44 AM UTC 24 |
Sep 01 09:11:31 AM UTC 24 |
38948469086 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3664342878 |
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Sep 01 09:11:08 AM UTC 24 |
Sep 01 09:11:35 AM UTC 24 |
22359445989 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.491459235 |
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Sep 01 09:11:11 AM UTC 24 |
Sep 01 09:11:38 AM UTC 24 |
22596919183 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.7540803 |
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Sep 01 09:09:53 AM UTC 24 |
Sep 01 09:11:39 AM UTC 24 |
29363675273 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2591293437 |
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Sep 01 09:10:38 AM UTC 24 |
Sep 01 09:11:44 AM UTC 24 |
61822627603 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1068800868 |
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Sep 01 09:11:12 AM UTC 24 |
Sep 01 09:11:46 AM UTC 24 |
54380634262 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.1053349290 |
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Sep 01 09:04:27 AM UTC 24 |
Sep 01 09:11:50 AM UTC 24 |
1385230086458 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1146757432 |
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Sep 01 09:10:52 AM UTC 24 |
Sep 01 09:11:52 AM UTC 24 |
34785994887 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2999294424 |
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Sep 01 09:11:32 AM UTC 24 |
Sep 01 09:11:54 AM UTC 24 |
25852204478 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.610177640 |
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Sep 01 09:11:33 AM UTC 24 |
Sep 01 09:11:55 AM UTC 24 |
28605968658 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3773054022 |
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Sep 01 09:11:36 AM UTC 24 |
Sep 01 09:11:56 AM UTC 24 |
26773114930 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.987396319 |
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Sep 01 09:10:55 AM UTC 24 |
Sep 01 09:11:56 AM UTC 24 |
51493074119 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.4120808153 |
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Sep 01 09:11:20 AM UTC 24 |
Sep 01 09:12:03 AM UTC 24 |
24338725586 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.653701276 |
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Sep 01 09:11:29 AM UTC 24 |
Sep 01 09:12:07 AM UTC 24 |
101263867700 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.4132383745 |
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Sep 01 09:10:34 AM UTC 24 |
Sep 01 09:12:08 AM UTC 24 |
88623719077 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2922334527 |
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Sep 01 09:10:00 AM UTC 24 |
Sep 01 09:12:09 AM UTC 24 |
124036038344 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2363976234 |
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Sep 01 09:11:18 AM UTC 24 |
Sep 01 09:12:13 AM UTC 24 |
39958960471 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2147855034 |
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Sep 01 09:11:20 AM UTC 24 |
Sep 01 09:12:14 AM UTC 24 |
53305894638 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1588247470 |
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Sep 01 09:07:05 AM UTC 24 |
Sep 01 09:12:18 AM UTC 24 |
93739264592 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1319739419 |
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Sep 01 09:11:23 AM UTC 24 |
Sep 01 09:12:21 AM UTC 24 |
42242950140 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.236641184 |
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Sep 01 09:10:44 AM UTC 24 |
Sep 01 09:12:26 AM UTC 24 |
100407346449 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1861267853 |
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Sep 01 09:11:45 AM UTC 24 |
Sep 01 09:12:28 AM UTC 24 |
52511198284 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3572004390 |
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Sep 01 09:11:05 AM UTC 24 |
Sep 01 09:12:34 AM UTC 24 |
66589693977 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.536510305 |
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Sep 01 09:10:46 AM UTC 24 |
Sep 01 09:12:36 AM UTC 24 |
24331062750 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2636650217 |
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Sep 01 09:06:15 AM UTC 24 |
Sep 01 09:12:55 AM UTC 24 |
118771458912 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.3694545867 |
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Sep 01 09:06:34 AM UTC 24 |
Sep 01 09:13:02 AM UTC 24 |
305444939129 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.20728742 |
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Sep 01 09:10:54 AM UTC 24 |
Sep 01 09:13:04 AM UTC 24 |
38425169211 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1708119588 |
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Sep 01 09:10:36 AM UTC 24 |
Sep 01 09:13:07 AM UTC 24 |
132476719121 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3453555781 |
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Sep 01 09:11:09 AM UTC 24 |
Sep 01 09:13:28 AM UTC 24 |
37199663389 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2519938143 |
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Sep 01 09:10:33 AM UTC 24 |
Sep 01 09:13:10 AM UTC 24 |
125982738224 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3405096876 |
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Sep 01 09:10:45 AM UTC 24 |
Sep 01 09:13:52 AM UTC 24 |
105963373889 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.2313637826 |
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|
Sep 01 09:10:23 AM UTC 24 |
Sep 01 09:14:02 AM UTC 24 |
148780764621 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1040579955 |
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Sep 01 09:10:37 AM UTC 24 |
Sep 01 09:14:18 AM UTC 24 |
72337914061 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.4294951485 |
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Sep 01 09:10:36 AM UTC 24 |
Sep 01 09:14:30 AM UTC 24 |
80345538778 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1340556867 |
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Sep 01 09:11:03 AM UTC 24 |
Sep 01 09:14:32 AM UTC 24 |
111784707076 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.703129649 |
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Sep 01 09:09:08 AM UTC 24 |
Sep 01 09:14:43 AM UTC 24 |
100637450419 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2604847544 |
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Sep 01 09:11:07 AM UTC 24 |
Sep 01 09:14:50 AM UTC 24 |
71258078851 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1349387766 |
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Sep 01 09:07:23 AM UTC 24 |
Sep 01 09:14:53 AM UTC 24 |
2673603673150 ps |
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/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.1538290104 |
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Sep 01 09:10:29 AM UTC 24 |
Sep 01 09:14:56 AM UTC 24 |
100218062241 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1533048859 |
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Sep 01 09:03:49 AM UTC 24 |
Sep 01 09:15:06 AM UTC 24 |
422699702028 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.2824503964 |
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Sep 01 09:07:45 AM UTC 24 |
Sep 01 09:15:11 AM UTC 24 |
130090217213 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3496660458 |
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Sep 01 09:11:27 AM UTC 24 |
Sep 01 09:15:28 AM UTC 24 |
120289891618 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3598978077 |
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Sep 01 09:09:50 AM UTC 24 |
Sep 01 09:15:32 AM UTC 24 |
124679796020 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2779964037 |
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Sep 01 09:09:54 AM UTC 24 |
Sep 01 09:15:35 AM UTC 24 |
122400459999 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.3077424643 |
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|
Sep 01 09:09:59 AM UTC 24 |
Sep 01 09:15:43 AM UTC 24 |
99682155639 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1031756927 |
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Sep 01 09:11:29 AM UTC 24 |
Sep 01 09:15:49 AM UTC 24 |
72946244331 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.1848455358 |
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Sep 01 09:08:00 AM UTC 24 |
Sep 01 09:15:53 AM UTC 24 |
148096412687 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2559718301 |
|
|
Sep 01 09:11:18 AM UTC 24 |
Sep 01 09:15:55 AM UTC 24 |
76486447495 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3270300826 |
|
|
Sep 01 09:11:39 AM UTC 24 |
Sep 01 09:16:27 AM UTC 24 |
69031462600 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.860538253 |
|
|
Sep 01 09:10:43 AM UTC 24 |
Sep 01 09:16:36 AM UTC 24 |
94354773358 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2367354982 |
|
|
Sep 01 09:11:05 AM UTC 24 |
Sep 01 09:16:43 AM UTC 24 |
114160438653 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3553408585 |
|
|
Sep 01 09:07:14 AM UTC 24 |
Sep 01 09:17:04 AM UTC 24 |
179357952363 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3289987509 |
|
|
Sep 01 09:10:15 AM UTC 24 |
Sep 01 09:17:12 AM UTC 24 |
119439685265 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2217834340 |
|
|
Sep 01 09:09:18 AM UTC 24 |
Sep 01 09:17:27 AM UTC 24 |
153256338216 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.860628989 |
|
|
Sep 01 09:08:19 AM UTC 24 |
Sep 01 09:17:54 AM UTC 24 |
150921431519 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3443922571 |
|
|
Sep 01 09:10:32 AM UTC 24 |
Sep 01 09:18:07 AM UTC 24 |
136120970939 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.785230439 |
|
|
Sep 01 09:11:43 AM UTC 24 |
Sep 01 09:18:30 AM UTC 24 |
135846194576 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3495272717 |
|
|
Sep 01 09:04:53 AM UTC 24 |
Sep 01 09:18:47 AM UTC 24 |
1287056450680 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.298560840 |
|
|
Sep 01 09:10:32 AM UTC 24 |
Sep 01 09:18:50 AM UTC 24 |
283016591666 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.930825989 |
|
|
Sep 01 09:08:47 AM UTC 24 |
Sep 01 09:19:04 AM UTC 24 |
193421481349 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.3344096219 |
|
|
Sep 01 09:06:23 AM UTC 24 |
Sep 01 09:39:23 AM UTC 24 |
517118794396 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2320018177 |
|
|
Sep 01 09:11:47 AM UTC 24 |
Sep 01 09:11:53 AM UTC 24 |
2242295654 ps |