Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	86.46	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_auto_blk_out_ctl_cg_(2)	79.17	1	100	1	64	64
sysrst_ctrl_auto_blk_out_ctl_cg_(1)	83.33	1	100	1	64	64
sysrst_ctrl_auto_blk_out_ctl_cg_(3)	83.33	1	100	1	64	64
sysrst_ctrl_auto_blk_out_ctl_cg	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(2)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.17	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	12	4	8	66.67

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	0	2	100.00	100	1	1	2
cp_key0_out_value	2	1	1	50.00	100	1	1	2
cp_key1_out_sel	2	0	2	100.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	0	2	100.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	2	2	50.00	100	1	1	0
cross_key1_out_sel_value	4	1	3	75.00	100	1	1	0
cross_key2_out_sel_value	4	1	3	75.00	100	1	1	0

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	12	4	8	66.67

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	0	2	100.00	100	1	1	2
cp_key0_out_value	2	0	2	100.00	100	1	1	2
cp_key1_out_sel	2	0	2	100.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	0	2	100.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	1	3	75.00	100	1	1	0
cross_key1_out_sel_value	4	2	2	50.00	100	1	1	0
cross_key2_out_sel_value	4	1	3	75.00	100	1	1	0

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(3)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	12	4	8	66.67

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	0	2	100.00	100	1	1	2
cp_key0_out_value	2	0	2	100.00	100	1	1	2
cp_key1_out_sel	2	0	2	100.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	0	2	100.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	1	3	75.00	100	1	1	0
cross_key1_out_sel_value	4	2	2	50.00	100	1	1	0
cross_key2_out_sel_value	4	1	3	75.00	100	1	1	0

---

Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	12	0	12	100.00

Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_key0_out_sel	2	0	2	100.00	100	1	1	2
cp_key0_out_value	2	0	2	100.00	100	1	1	2
cp_key1_out_sel	2	0	2	100.00	100	1	1	2
cp_key1_out_value	2	0	2	100.00	100	1	1	2
cp_key2_out_sel	2	0	2	100.00	100	1	1	2
cp_key2_out_value	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key0_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key1_out_sel_value	4	0	4	100.00	100	1	1	0
cross_key2_out_sel_value	4	0	4	100.00	100	1	1	0

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	2	1			T115	2
auto[1]	1	1			T115	1

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_key0_out_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	3	1			T115	3

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T115	1
auto[1]	2	1			T115	2

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T115	1
auto[1]	2	1			T115	2

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T115	1
auto[1]	2	1			T115	2

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T115	1
auto[1]	2	1			T115	2

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cross_key0_out_sel_value

Element holes

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	2

Covered bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	2	1			T115	2
auto[0]	auto[1]	1	1			T115	1

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cross_key1_out_sel_value

Uncovered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	0	1	1

Covered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[1]	1	1			T115	1
auto[1]	auto[0]	1	1			T115	1
auto[1]	auto[1]	1	1			T115	1

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	0	1	1

Covered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[1]	1	1			T115	1
auto[1]	auto[0]	1	1			T115	1
auto[1]	auto[1]	1	1			T115	1

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T446	1
auto[1]	2	1			T446	2

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	2	1			T446	2
auto[1]	1	1			T446	1

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T446	1
auto[1]	2	1			T446	2

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T446	1
auto[1]	2	1			T446	2

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	2	1			T446	2
auto[1]	1	1			T446	1

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T446	1
auto[1]	2	1			T446	2

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cross_key0_out_sel_value

Uncovered bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	1	1			T446	1
auto[0]	auto[1]	1	1			T446	1
auto[1]	auto[1]	1	1			T446	1

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cross_key1_out_sel_value

Uncovered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	1	1			T446	1
auto[1]	auto[1]	2	1			T446	2

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	1	1			T446	1
auto[1]	auto[0]	1	1			T446	1
auto[1]	auto[1]	1	1			T446	1

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T115	1
auto[1]	2	1			T115	2

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	2	1			T115	2
auto[1]	1	1			T115	1

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	2	1			T115	2
auto[1]	1	1			T115	1

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	2	1			T115	2
auto[1]	1	1			T115	1

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_sel

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	1	1			T115	1
auto[1]	2	1			T115	2

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	2	1			T115	2
auto[1]	1	1			T115	1

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cross_key0_out_sel_value

Uncovered bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_key0_out_value	cp_key0_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	1	1			T115	1
auto[0]	auto[1]	1	1			T115	1
auto[1]	auto[1]	1	1			T115	1

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cross_key1_out_sel_value

Uncovered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_key1_out_value	cp_key1_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	2	1			T115	2
auto[1]	auto[1]	1	1			T115	1

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_key2_out_value	cp_key2_out_sel	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	1	1			T115	1
auto[0]	auto[1]	1	1			T115	1
auto[1]	auto[1]	1	1			T115	1

Summary for Variable cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83

1

T16

1

T26

2

T58

2

auto[1]

92

1

T16

2

T26

1

T27

3

---

Summary for Variable cp_key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69

1

T16

1

T26

2

T27

2

auto[1]

106

1

T16

2

T26

1

T27

1

---

Summary for Variable cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90

1

T16

2

T27

3

T58

2

auto[1]

85

1

T16

1

T26

3

T58

1

---

Summary for Variable cp_key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83

1

T16

1

T27

2

T60

2

auto[1]

92

1

T16

2

T26

3

T27

1

---

Summary for Variable cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91

1

T16

1

T27

2

T58

1

auto[1]

84

1

T16

2

T26

3

T27

1

---

Summary for Variable cp_key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93

1

T16

3

T26

2

T27

1

auto[1]

82

1

T26

1

T27

2

T58

1

---

Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins

cp_key0_out_value

cp_key0_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

33

1

T16

1

T26

2

T58

2

auto[0]

auto[1]

36

1

T27

2

T60

1

T63

1

auto[1]

auto[0]

50

1

T60

1

T61

1

T63

1

auto[1]

auto[1]

56

1

T16

2

T26

1

T27

1

---

Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins

cp_key1_out_value

cp_key1_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

42

1

T16

1

T27

2

T60

1

auto[0]

auto[1]

41

1

T60

1

T61

2

T65

2

auto[1]

auto[0]

48

1

T16

1

T27

1

T58

2

auto[1]

auto[1]

44

1

T16

1

T26

3

T58

1

---

Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins

cp_key2_out_value

cp_key2_out_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

49

1

T16

1

T27

1

T58

1

auto[0]

auto[1]

44

1

T16

2

T26

2

T58

1

auto[1]

auto[0]

42

1

T27

1

T61

1

T64

1

auto[1]

auto[1]

40

1

T26

1

T27

1

T58

1