Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1934

1

T33

5

T30

16

T40

7

auto[1]

540

1

T33

5

T40

8

T55

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1889

1

T33

9

T30

16

T40

10

auto[1]

585

1

T33

1

T40

5

T103

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1822

1

T33

1

T30

16

T40

4

auto[1]

652

1

T33

9

T40

11

T55

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1965

1

T33

5

T30

12

T40

5

auto[1]

509

1

T33

5

T30

4

T40

10

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2254

1

T33

10

T30

12

T40

15

auto[1]

220

1

T30

4

T96

2

T125

5

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2215

1

T33

10

T30

12

T40

15

auto[1]

259

1

T30

4

T41

4

T96

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2342

1

T33

10

T30

16

T40

15

auto[1]

132

1

T41

2

T97

4

T273

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2216

1

T33

10

T30

16

T40

15

auto[1]

258

1

T41

2

T97

4

T271

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2257

1

T33

10

T30

16

T40

15

auto[1]

217

1

T41

1

T56

1

T96

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1807

1

T30

16

T40

8

T42

21

auto[1]

667

1

T33

10

T40

7

T55

5

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[0]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	833	1			T33	10		T40	15		T55	5
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	65	1			T273	2		T279	3		T406	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	78	1			T41	1		T56	1		T381	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	18	1			T407	7		T408	5		T397	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	57	1			T271	2		T122	4		T278	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	19	1			T189	1		T409	1		T398	17
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	35	1			T410	2		T411	9		T412	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	12	1			T413	1		T414	3		T415	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	37	1			T273	3		T183	1		T416	10
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	7	1			T414	4		T408	3		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T396	3		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T388	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	29	1			T97	4		T305	11		T417	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T270	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	13	1			T418	4		T419	5		T420	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	96	1			T271	2		T272	6		T126	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	41	1			T189	1		T421	4		T422	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	11	1			T406	2		T423	3		T415	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	2	1			T96	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	30	1			T41	1		T406	2		T424	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	15	1			T425	8		T426	5		T427	2
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T428	2		T429	3		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	16	1			T41	1		T305	9		T414	1
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T430	4		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T431	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T421	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

78

1

T381

2

T382

7

T305

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

143

1

T42

13

T378

12

T305

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

49

1

T268

11

T122

4

T302

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

90

1

T268

12

T96

2

T294

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

52

1

T289

2

T315

8

T395

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T40

4

T41

1

T124

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

35

1

T55

2

T289

1

T272

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

127

1

T183

5

T188

10

T385

13

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

47

1

T42

4

T272

3

T315

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

105

1

T55

3

T271

2

T273

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T33

4

T41

1

T315

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T294

5

T432

5

T395

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

46

1

T40

6

T379

5

T406

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T33

5

T302

2

T383

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T379

2

T395

1

T433

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

115

1

T97

4

T189

1

T385

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

39

1

T42

3

T381

2

T383

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

83

1

T273

1

T278

1

T218

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T33

1

T294

3

T124

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

12

1

T279

3

T290

5

T434

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T383

4

T291

3

T129

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T268

12

T273

1

T435

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T103

1

T273

1

T134

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

64

1

T379

5

T384

5

T304

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

40

1

T40

2

T41

1

T271

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T40

3

T124

4

T377

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T377

2

T385

1

T304

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

21

1

T56

1

T287

2

T218

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T436

1

T388

4

T308

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T437

1

T308

4

T389

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T130

1

T438

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded