Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609

1

T24

8

T25

9

T90

7

auto[1]

608

1

T24

12

T25

11

T90

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

286

1

T24

5

T25

4

T90

3

from_0to1

290

1

T24

5

T25

5

T90

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609

1

T24

10

T25

11

T90

13

auto[1]

608

1

T24

10

T25

9

T90

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

599

1

T24

8

T25

11

T90

10

auto[1]

618

1

T24

12

T25

9

T90

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T91

1

T93

1

T105

1

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T25

1

T91

1

T93

2

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T24

1

T91

1

T206

1

auto[0]

from_1to0

auto[1]

auto[1]

33

1

T24

1

T25

1

T90

1

auto[0]

from_0to1

auto[0]

auto[0]

27

1

T24

1

T25

1

T93

2

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T24

1

T90

1

T91

1

auto[0]

from_0to1

auto[1]

auto[0]

31

1

T24

1

T90

1

T295

1

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T25

1

T91

2

T105

1

auto[1]

from_1to0

auto[0]

auto[0]

36

1

T25

1

T206

1

T275

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T24

2

T90

1

T105

2

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T25

1

T90

1

T105

1

auto[1]

from_1to0

auto[1]

auto[1]

26

1

T24

1

T91

1

T93

1

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T25

1

T91

2

T295

1

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T24

1

T93

1

T105

1

auto[1]

from_0to1

auto[1]

auto[0]

35

1

T24

1

T25

1

T105

1

auto[1]

from_0to1

auto[1]

auto[1]

37

1

T25

1

T90

1

T105

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

598

1

T24

5

T25

11

T90

9

auto[1]

619

1

T24

15

T25

9

T90

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

288

1

T24

3

T25

6

T90

2

from_0to1

293

1

T24

3

T25

5

T90

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

601

1

T24

11

T25

8

T90

7

auto[1]

616

1

T24

9

T25

12

T90

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

608

1

T24

13

T25

13

T90

12

auto[1]

609

1

T24

7

T25

7

T90

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T24

1

T206

1

T195

1

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T25

2

T91

1

T93

1

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T25

2

T93

1

T295

1

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T93

2

T295

1

T206

1

auto[0]

from_0to1

auto[0]

auto[0]

26

1

T25

1

T91

1

T93

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T25

1

T105

1

T195

1

auto[0]

from_0to1

auto[1]

auto[0]

27

1

T25

1

T90

1

T91

1

auto[0]

from_0to1

auto[1]

auto[1]

42

1

T24

1

T25

1

T93

1

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T90

1

T91

1

T93

2

auto[1]

from_1to0

auto[0]

auto[1]

26

1

T24

1

T105

2

T451

1

auto[1]

from_1to0

auto[1]

auto[0]

35

1

T24

1

T25

1

T91

2

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T25

1

T90

1

T91

1

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T91

1

T93

2

T295

1

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T24

2

T91

1

T93

1

auto[1]

from_0to1

auto[1]

auto[0]

35

1

T25

1

T91

1

T105

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T90

1

T93

1

T105

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

590

1

T24

8

T25

11

T90

5

auto[1]

627

1

T24

12

T25

9

T90

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

292

1

T24

5

T25

3

T90

5

from_0to1

295

1

T24

5

T25

3

T90

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

593

1

T24

11

T25

8

T90

12

auto[1]

624

1

T24

9

T25

12

T90

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

593

1

T24

8

T25

8

T90

11

auto[1]

624

1

T24

12

T25

12

T90

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T24

1

T25

1

T105

1

auto[0]

from_1to0

auto[0]

auto[1]

34

1

T24

1

T25

1

T90

2

auto[0]

from_1to0

auto[1]

auto[0]

30

1

T91

1

T93

1

T105

1

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T25

1

T93

1

T105

1

auto[0]

from_0to1

auto[0]

auto[0]

30

1

T24

1

T91

1

T295

1

auto[0]

from_0to1

auto[0]

auto[1]

41

1

T24

1

T93

1

T206

1

auto[0]

from_0to1

auto[1]

auto[0]

34

1

T90

1

T98

1

T206

1

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T91

3

T206

1

T276

1

auto[1]

from_1to0

auto[0]

auto[0]

32

1

T24

1

T90

1

T91

2

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T91

1

T93

2

T98

1

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T24

1

T90

2

T91

2

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T24

1

T91

1

T206

1

auto[1]

from_0to1

auto[0]

auto[0]

32

1

T24

1

T90

2

T105

1

auto[1]

from_0to1

auto[0]

auto[1]

30

1

T24

1

T90

1

T91

1

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T25

1

T90

1

T91

1

auto[1]

from_0to1

auto[1]

auto[1]

44

1

T24

1

T25

2

T91

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

615

1

T24

9

T25

11

T90

9

auto[1]

602

1

T24

11

T25

9

T90

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

292

1

T24

5

T25

4

T90

6

from_0to1

295

1

T24

5

T25

5

T90

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623

1

T24

15

T25

11

T90

13

auto[1]

594

1

T24

5

T25

9

T90

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

615

1

T24

8

T25

13

T90

8

auto[1]

602

1

T24

12

T25

7

T90

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T24

1

T25

1

T98

1

auto[0]

from_1to0

auto[0]

auto[1]

44

1

T24

1

T90

2

T93

1

auto[0]

from_1to0

auto[1]

auto[0]

38

1

T25

1

T91

2

T105

1

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T91

1

T93

2

T105

1

auto[0]

from_0to1

auto[0]

auto[0]

44

1

T90

1

T98

1

T275

2

auto[0]

from_0to1

auto[0]

auto[1]

42

1

T24

1

T25

1

T90

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T24

1

T25

2

T90

1

auto[0]

from_0to1

auto[1]

auto[1]

20

1

T91

1

T105

1

T98

1

auto[1]

from_1to0

auto[0]

auto[0]

35

1

T25

1

T90

2

T105

2

auto[1]

from_1to0

auto[0]

auto[1]

28

1

T24

2

T25

1

T98

1

auto[1]

from_1to0

auto[1]

auto[0]

31

1

T90

1

T295

2

T206

1

auto[1]

from_1to0

auto[1]

auto[1]

34

1

T24

1

T90

1

T91

1

auto[1]

from_0to1

auto[0]

auto[0]

32

1

T90

1

T93

1

T295

1

auto[1]

from_0to1

auto[0]

auto[1]

46

1

T24

3

T25

1

T90

1

auto[1]

from_0to1

auto[1]

auto[0]

35

1

T25

1

T105

1

T206

1

auto[1]

from_0to1

auto[1]

auto[1]

33

1

T91

1

T295

1

T98

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

618

1

T24

7

T25

10

T90

9

auto[1]

599

1

T24

13

T25

10

T90

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

310

1

T24

3

T25

6

T90

3

from_0to1

308

1

T24

3

T25

6

T90

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

595

1

T24

10

T25

11

T90

9

auto[1]

622

1

T24

10

T25

9

T90

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

608

1

T24

13

T25

13

T90

11

auto[1]

609

1

T24

7

T25

7

T90

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T24

1

T93

1

T295

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T25

2

T93

1

T295

1

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T25

2

T90

1

T91

2

auto[0]

from_1to0

auto[1]

auto[1]

45

1

T24

1

T91

2

T93

2

auto[0]

from_0to1

auto[0]

auto[0]

27

1

T25

2

T105

1

T295

2

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T90

1

T295

1

T98

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T25

1

T93

1

T98

2

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T91

1

T93

2

T105

1

auto[1]

from_1to0

auto[0]

auto[0]

29

1

T90

1

T91

1

T93

1

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T24

1

T105

1

T295

1

auto[1]

from_1to0

auto[1]

auto[0]

36

1

T25

2

T93

1

T105

1

auto[1]

from_1to0

auto[1]

auto[1]

34

1

T90

1

T91

1

T276

1

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T24

2

T25

1

T90

1

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T25

1

T91

1

T93

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T24

1

T90

1

T91

1

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T25

1

T90

1

T91

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

605

1

T24

10

T25

7

T90

11

auto[1]

612

1

T24

10

T25

13

T90

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

293

1

T24

4

T25

5

T90

6

from_0to1

296

1

T24

4

T25

6

T90

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

587

1

T24

6

T25

6

T90

10

auto[1]

630

1

T24

14

T25

14

T90

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

600

1

T24

14

T25

10

T90

7

auto[1]

617

1

T24

6

T25

10

T90

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

33

1

T24

1

T93

1

T105

1

auto[0]

from_1to0

auto[0]

auto[1]

32

1

T91

1

T206

1

T195

1

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T24

2

T25

2

T90

1

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T25

1

T105

1

T295

1

auto[0]

from_0to1

auto[0]

auto[0]

46

1

T24

1

T90

2

T93

1

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T90

2

T105

1

T98

1

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T90

1

T91

1

T295

1

auto[0]

from_0to1

auto[1]

auto[1]

29

1

T25

1

T91

1

T195

1

auto[1]

from_1to0

auto[0]

auto[0]

35

1

T25

1

T90

1

T93

1

auto[1]

from_1to0

auto[0]

auto[1]

27

1

T90

1

T105

2

T295

1

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T24

1

T25

1

T91

3

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T90

3

T105

1

T295

3

auto[1]

from_0to1

auto[0]

auto[0]

23

1

T91

1

T98

1

T195

1

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T25

1

T105

2

T295

2

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T24

2

T25

2

T91

2

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T24

1

T25

2

T90

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

571

1

T24

12

T25

12

T90

7

auto[1]

646

1

T24

8

T25

8

T90

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

288

1

T24

5

T25

5

T90

5

from_0to1

281

1

T24

4

T25

4

T90

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

614

1

T24

10

T25

10

T90

11

auto[1]

603

1

T24

10

T25

10

T90

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609

1

T24

14

T25

11

T90

11

auto[1]

608

1

T24

6

T25

9

T90

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

24

1

T24

1

T276

1

T313

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T25

1

T93

1

T98

1

auto[0]

from_1to0

auto[1]

auto[0]

35

1

T24

2

T25

2

T91

1

auto[0]

from_1to0

auto[1]

auto[1]

24

1

T24

1

T25

1

T90

1

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T24

1

T25

2

T90

1

auto[0]

from_0to1

auto[0]

auto[1]

43

1

T25

1

T90

1

T105

3

auto[0]

from_0to1

auto[1]

auto[0]

29

1

T24

1

T25

1

T91

1

auto[0]

from_0to1

auto[1]

auto[1]

34

1

T24

1

T295

1

T98

2

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T90

2

T105

2

T295

3

auto[1]

from_1to0

auto[0]

auto[1]

29

1

T91

1

T93

1

T105

1

auto[1]

from_1to0

auto[1]

auto[0]

46

1

T24

1

T25

1

T90

1

auto[1]

from_1to0

auto[1]

auto[1]

41

1

T90

1

T91

2

T93

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T24

1

T90

2

T91

2

auto[1]

from_0to1

auto[0]

auto[1]

34

1

T90

1

T91

1

T195

2

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T90

1

T93

2

T105

1

auto[1]

from_0to1

auto[1]

auto[1]

36

1

T105

1

T98

1

T195

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

614

1

T24

12

T25

12

T90

11

auto[1]

603

1

T24

8

T25

8

T90

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

300

1

T24

4

T25

3

T90

5

from_0to1

300

1

T24

4

T25

4

T90

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

602

1

T24

9

T25

9

T90

12

auto[1]

615

1

T24

11

T25

11

T90

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

634

1

T24

12

T25

8

T90

11

auto[1]

583

1

T24

8

T25

12

T90

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

47

1

T24

1

T25

1

T90

3

auto[0]

from_1to0

auto[0]

auto[1]

27

1

T90

1

T295

1

T98

1

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T25

1

T91

2

T93

4

auto[0]

from_1to0

auto[1]

auto[1]

36

1

T24

1

T105

1

T98

1

auto[0]

from_0to1

auto[0]

auto[0]

35

1

T24

1

T90

1

T295

1

auto[0]

from_0to1

auto[0]

auto[1]

35

1

T25

1

T90

1

T206

2

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T93

1

T105

1

T206

2

auto[0]

from_0to1

auto[1]

auto[1]

37

1

T24

1

T25

1

T91

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T25

1

T93

3

T98

1

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T24

1

T105

2

T295

2

auto[1]

from_1to0

auto[1]

auto[0]

32

1

T24

1

T91

2

T295

2

auto[1]

from_1to0

auto[1]

auto[1]

30

1

T90

1

T206

1

T276

1

auto[1]

from_0to1

auto[0]

auto[0]

37

1

T24

1

T93

1

T295

1

auto[1]

from_0to1

auto[0]

auto[1]

39

1

T90

2

T91

1

T93

2

auto[1]

from_0to1

auto[1]

auto[0]

38

1

T25

1

T91

1

T105

3

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T24

1

T25

1

T91

1