Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	143970	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

112135

1

T1

5

T4

8

T5

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	133792	1			T1	4		T4	18		T5	3
values[0x0]	60465	1			T1	3		T5	4		T13	1
values[0x1]	61848	1			T1	4		T4	1		T5	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	116603	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

139502

1

T1

7

T4

9

T5

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	942	1			T89	1		T93	1		T83	2
valid_sources[0x01]	752	1			T7	1		T25	4		T89	1
valid_sources[0x02]	787	1			T7	1		T25	2		T23	1
valid_sources[0x03]	898	1			T24	3		T10	1		T94	5
valid_sources[0x04]	829	1			T25	7		T22	4		T147	1
valid_sources[0x05]	859	1			T2	1		T24	7		T9	3
valid_sources[0x06]	1666	1			T25	4		T9	1		T91	2
valid_sources[0x07]	878	1			T16	1		T24	5		T25	1
valid_sources[0x08]	759	1			T3	1		T79	1		T12	3
valid_sources[0x09]	825	1			T1	1		T26	1		T25	19
valid_sources[0x0a]	781	1			T90	5		T10	1		T161	20
valid_sources[0x0b]	837	1			T9	6		T89	1		T10	1
valid_sources[0x0c]	820	1			T2	1		T14	1		T24	1
valid_sources[0x0d]	902	1			T14	1		T26	1		T79	2
valid_sources[0x0e]	1176	1			T24	2		T25	7		T90	1
valid_sources[0x0f]	898	1			T90	2		T69	1		T83	1
valid_sources[0x10]	992	1			T24	3		T9	2		T107	1
valid_sources[0x11]	712	1			T2	1		T27	1		T9	3
valid_sources[0x12]	869	1			T26	2		T9	4		T106	1
valid_sources[0x13]	783	1			T2	1		T22	3		T67	2
valid_sources[0x14]	745	1			T9	1		T182	1		T93	2
valid_sources[0x15]	860	1			T3	1		T90	1		T94	1
valid_sources[0x16]	730	1			T7	1		T24	1		T26	1
valid_sources[0x17]	947	1			T24	4		T93	1		T33	4
valid_sources[0x18]	1844	1			T93	3		T33	4		T62	1
valid_sources[0x19]	1420	1			T25	12		T181	1		T93	1
valid_sources[0x1a]	1880	1			T26	2		T25	5		T89	1
valid_sources[0x1b]	770	1			T93	1		T33	3		T164	1
valid_sources[0x1c]	758	1			T3	2		T90	2		T33	3
valid_sources[0x1d]	675	1			T93	1		T33	5		T62	1
valid_sources[0x1e]	931	1			T24	1		T67	3		T9	9
valid_sources[0x1f]	966	1			T7	1		T94	1		T69	1
valid_sources[0x20]	1631	1			T33	1		T62	1		T29	3
valid_sources[0x21]	736	1			T25	6		T9	3		T33	2
valid_sources[0x22]	852	1			T9	5		T93	2		T33	1
valid_sources[0x23]	1174	1			T24	2		T83	1		T107	2
valid_sources[0x24]	960	1			T2	1		T15	63		T25	4
valid_sources[0x25]	768	1			T24	4		T28	1		T10	1
valid_sources[0x26]	794	1			T14	1		T91	36		T28	1
valid_sources[0x27]	1828	1			T107	1		T33	2		T29	4
valid_sources[0x28]	930	1			T16	2		T24	1		T22	2
valid_sources[0x29]	862	1			T14	1		T9	1		T17	23
valid_sources[0x2a]	1537	1			T14	2		T93	2		T69	1
valid_sources[0x2b]	734	1			T24	2		T104	2		T165	3
valid_sources[0x2c]	778	1			T24	2		T10	2		T62	1
valid_sources[0x2d]	790	1			T16	1		T9	4		T90	8
valid_sources[0x2e]	780	1			T24	3		T26	3		T9	2
valid_sources[0x2f]	1490	1			T5	2		T16	1		T11	1
valid_sources[0x30]	1944	1			T5	1		T24	3		T25	1
valid_sources[0x31]	1002	1			T22	2		T91	1		T93	3
valid_sources[0x32]	756	1			T14	1		T10	1		T33	3
valid_sources[0x33]	1682	1			T27	1		T11	1		T93	1
valid_sources[0x34]	867	1			T1	2		T25	2		T9	2
valid_sources[0x35]	946	1			T14	1		T27	1		T9	5
valid_sources[0x36]	793	1			T26	1		T9	2		T90	4
valid_sources[0x37]	931	1			T26	1		T25	4		T89	1
valid_sources[0x38]	1417	1			T90	1		T107	1		T62	1
valid_sources[0x39]	1250	1			T14	1		T26	3		T32	399
valid_sources[0x3a]	881	1			T1	1		T14	1		T16	1
valid_sources[0x3b]	1009	1			T26	1		T9	4		T161	20
valid_sources[0x3c]	752	1			T2	1		T9	1		T147	1
valid_sources[0x3d]	1055	1			T3	1		T22	2		T9	4
valid_sources[0x3e]	777	1			T1	1		T9	1		T93	2
valid_sources[0x3f]	808	1			T2	1		T9	5		T147	1
valid_sources[0x40]	886	1			T10	1		T69	1		T33	1
valid_sources[0x41]	864	1			T26	1		T9	2		T90	1
valid_sources[0x42]	2056	1			T7	1		T9	1		T6	1
valid_sources[0x43]	759	1			T25	4		T33	5		T62	1
valid_sources[0x44]	783	1			T9	1		T23	5		T335	2
valid_sources[0x45]	811	1			T161	20		T62	1		T85	1
valid_sources[0x46]	709	1			T24	2		T26	1		T9	7
valid_sources[0x47]	779	1			T26	1		T12	2		T62	1
valid_sources[0x48]	1916	1			T9	3		T106	1		T61	1
valid_sources[0x49]	767	1			T2	2		T14	1		T83	1
valid_sources[0x4a]	1256	1			T8	11		T9	2		T17	20
valid_sources[0x4b]	1268	1			T9	15		T12	4		T107	1
valid_sources[0x4c]	919	1			T23	1		T107	1		T33	2
valid_sources[0x4d]	744	1			T25	6		T9	1		T91	3
valid_sources[0x4e]	768	1			T9	1		T121	1		T149	1
valid_sources[0x4f]	852	1			T26	3		T9	2		T121	1
valid_sources[0x50]	870	1			T14	1		T25	8		T69	1
valid_sources[0x51]	1060	1			T7	1		T90	1		T10	1
valid_sources[0x52]	741	1			T66	1		T83	2		T61	1
valid_sources[0x53]	856	1			T14	2		T82	44		T33	2
valid_sources[0x54]	804	1			T91	75		T10	1		T149	4
valid_sources[0x55]	830	1			T2	1		T16	1		T9	1
valid_sources[0x56]	790	1			T9	2		T107	1		T164	1
valid_sources[0x57]	719	1			T90	4		T12	3		T94	3
valid_sources[0x58]	1137	1			T26	1		T104	1		T84	1
valid_sources[0x59]	1623	1			T16	2		T9	2		T93	1
valid_sources[0x5a]	867	1			T24	2		T9	2		T91	5
valid_sources[0x5b]	753	1			T91	4		T10	1		T93	5
valid_sources[0x5c]	1000	1			T2	2		T24	4		T9	1
valid_sources[0x5d]	810	1			T67	2		T181	1		T10	1
valid_sources[0x5e]	841	1			T7	2		T89	3		T90	6
valid_sources[0x5f]	872	1			T90	1		T182	1		T149	1
valid_sources[0x60]	876	1			T14	1		T91	20		T10	1
valid_sources[0x61]	911	1			T84	1		T161	20		T33	1
valid_sources[0x62]	886	1			T9	2		T62	4		T452	6
valid_sources[0x63]	1110	1			T13	1		T2	2		T24	1
valid_sources[0x64]	869	1			T1	2		T22	7		T89	1
valid_sources[0x65]	871	1			T25	1		T93	1		T83	1
valid_sources[0x66]	1595	1			T14	4		T24	1		T9	5
valid_sources[0x67]	708	1			T24	1		T121	1		T89	1
valid_sources[0x68]	831	1			T9	1		T23	2		T83	1
valid_sources[0x69]	1689	1			T25	6		T9	1		T17	1
valid_sources[0x6a]	849	1			T14	1		T89	4		T6	1
valid_sources[0x6b]	641	1			T5	1		T121	1		T83	1
valid_sources[0x6c]	1370	1			T3	1		T24	3		T26	1
valid_sources[0x6d]	1735	1			T3	1		T91	2		T93	1
valid_sources[0x6e]	1680	1			T5	1		T22	4		T9	3
valid_sources[0x6f]	862	1			T2	1		T3	1		T9	2
valid_sources[0x70]	716	1			T2	1		T7	1		T89	1
valid_sources[0x71]	680	1			T9	2		T121	1		T72	1
valid_sources[0x72]	874	1			T150	1		T72	2		T33	4
valid_sources[0x73]	777	1			T14	1		T67	3		T90	2
valid_sources[0x74]	734	1			T25	1		T89	2		T23	1
valid_sources[0x75]	773	1			T90	1		T93	1		T84	1
valid_sources[0x76]	1746	1			T14	2		T9	3		T89	1
valid_sources[0x77]	710	1			T16	1		T25	3		T67	1
valid_sources[0x78]	774	1			T1	1		T2	1		T25	1
valid_sources[0x79]	745	1			T24	1		T121	1		T83	1
valid_sources[0x7a]	865	1			T83	1		T72	1		T33	5
valid_sources[0x7b]	793	1			T3	1		T24	4		T9	4
valid_sources[0x7c]	940	1			T16	1		T24	1		T26	6
valid_sources[0x7d]	891	1			T24	4		T26	1		T10	1
valid_sources[0x7e]	933	1			T14	1		T90	1		T91	22
valid_sources[0x7f]	829	1			T9	1		T6	4		T147	1
valid_sources[0x80]	2772	1			T2	1		T14	1		T24	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61248

1

T1

3

T4

7

T5

1

values[0x0]

all_enables

biggest_size

29609

1

T1

2

T5

3

T2

3

values[0x1]

all_enables

biggest_size

21278

1

T4

1

T5

2

T2

2