Unified Coverage Report :: Group :: tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_auto_block_debounce_ctl_cg

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_auto_block_debounce_ctl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_auto_block_debounce_ctl_cg	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_auto_block_debounce_ctl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_auto_block_debounce_ctl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00

Variables for Group Instance sysrst_ctrl_auto_block_debounce_ctl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_auto_block_enable	2	0	2	100.00	100	1	1	2
cp_debounce_timer	3	0	3	100.00	100	1	1	0

Summary for Variable cp_auto_block_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_auto_block_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

836

1

T16

8

T26

8

T27

2

auto[1]

778

1

T16

4

T26

4

T27

12

---

Summary for Variable cp_debounce_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_debounce_timer

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_range	1124	1			T16	6		T26	6		T27	8
mid_range	240	1			T16	4		T26	4		T27	4
min_range	250	1			T16	2		T26	2		T27	2