Unified Coverage Report :: Group :: tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_combo_precondition_det_cg

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_combo_precondition_det_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	91.67	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_precondition_det_cg0	66.67	1	100	1	64	64
sysrst_ctrl_combo_precondition_det_cg1	100.00	1	100	1	64	64
sysrst_ctrl_combo_precondition_det_cg2	100.00	1	100	1	64	64
sysrst_ctrl_combo_precondition_det_cg3	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.67	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	1	2	66.67

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	1	2	66.67	100	1	1	0

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	0	3	100.00	100	1	1	0

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	0	3	100.00	100	1	1	0

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	0	3	100.00	100	1	1	0

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_precondition_timer

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
mid_range	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max_range

24

1

T285

1

T415

8

T445

5

min_range

330

1

T31

1

T20

7

T32

1

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_precondition_timer

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_range	12	1			T446	1		T447	1		T448	10
mid_range	6	1			T449	6		-	-		-	-
min_range	336	1			T31	1		T20	7		T32	1

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_precondition_timer

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_range	12	1			T450	4		T408	4		T451	4
mid_range	2	1			T452	2		-	-		-	-
min_range	340	1			T31	1		T20	7		T32	1

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_precondition_timer

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_range	5	1			T214	4		T453	1		-	-
mid_range	7	1			T43	3		T280	4		-	-
min_range	341	1			T31	1		T20	7		T32	1