Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1921

1

T33

2

T42

12

T58

19

auto[1]

538

1

T33

3

T42

4

T58

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1884

1

T33

3

T42

16

T58

19

auto[1]

575

1

T33

2

T58

1

T40

8

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1852

1

T33

2

T42

16

T58

16

auto[1]

607

1

T33

3

T58

4

T40

13

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1859

1

T33

3

T42

16

T58

20

auto[1]

600

1

T33

2

T40

11

T41

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2268

1

T33

5

T42

16

T58

16

auto[1]

191

1

T58

4

T41

8

T282

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2229

1

T33

5

T42

14

T58

16

auto[1]

230

1

T42

2

T58

4

T43

7

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2261

1

T33

5

T42

14

T58

19

auto[1]

198

1

T42

2

T58

1

T43

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2191

1

T33

5

T42

14

T58

19

auto[1]

268

1

T42

2

T58

1

T43

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2224

1

T33

5

T42

16

T58

20

auto[1]

235

1

T41

5

T44

10

T142

14

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1853

1

T42

16

T58

20

T40

18

auto[1]

606

1

T33

5

T40

3

T43

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

843

1

T33

5

T40

21

T112

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

63

1

T271

2

T306

2

T118

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

72

1

T41

5

T44

5

T142

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T271

2

T412

1

T413

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T41

9

T320

3

T214

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T126

4

T414

1

T411

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T142

6

T285

1

T281

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T282

3

T320

3

T415

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T42

2

T400

5

T284

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T279

2

T409

6

T411

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

18

1

T285

1

T400

3

T416

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T417

1

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T58

1

T43

3

T142

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T118

1

T408

6

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T400

2

T418

4

T408

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

99

1

T43

4

T142

6

T400

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T419

2

T420

2

T409

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34

1

T44

5

T421

6

T410

13

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

20

1

T42

2

T43

3

T117

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T41

6

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1

1

T422

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T420

2

T423

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

13

1

T424

3

T406

8

T417

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T41

2

T421

5

T414

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T280

3

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

105

1

T42

4

T43

3

T114

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

152

1

T41

15

T142

5

T307

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

44

1

T43

4

T182

7

T284

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

151

1

T41

2

T325

10

T321

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T285

1

T402

3

T425

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T325

3

T326

7

T323

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T321

1

T288

2

T309

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

119

1

T142

14

T45

14

T320

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

58

1

T40

10

T43

3

T142

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

20

1

T326

4

T419

1

T426

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

53

1

T33

3

T45

5

T117

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

81

1

T44

5

T287

4

T306

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T307

1

T402

2

T308

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40

1

T40

3

T326

2

T324

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T287

2

T46

1

T403

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

91

1

T285

1

T271

3

T322

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

53

1

T58

1

T112

3

T400

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T271

2

T118

1

T128

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T284

3

T128

1

T427

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T40

8

T44

5

T182

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T46

4

T403

5

T237

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T33

2

T46

1

T401

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T428

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T41

5

T282

3

T427

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T429

3

T401

4

T320

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T325

1

T126

4

T401

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T307

1

T287

3

T322

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

8

1

T271

2

T429

1

T403

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T182

1

T321

2

T322

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T404

1

T128

1

T430

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T431

2

T136

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded