Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

644

1

T16

8

T26

15

T86

8

auto[1]

643

1

T16

12

T26

5

T86

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

314

1

T16

4

T26

4

T86

4

from_0to1

312

1

T16

4

T26

5

T86

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T16

7

T26

12

T86

8

auto[1]

645

1

T16

13

T26

8

T86

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623

1

T16

13

T26

13

T86

9

auto[1]

664

1

T16

7

T26

7

T86

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

37

1

T16

1

T155

2

T104

1

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T16

1

T86

1

T99

1

auto[0]

from_1to0

auto[1]

auto[0]

37

1

T86

1

T99

1

T361

1

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T155

1

T361

1

T97

1

auto[0]

from_0to1

auto[0]

auto[0]

32

1

T26

2

T86

1

T361

1

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T26

2

T99

1

T97

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T16

1

T155

3

T361

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T86

2

T99

1

T361

2

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T26

2

T99

2

T155

1

auto[1]

from_1to0

auto[0]

auto[1]

37

1

T86

1

T361

2

T461

2

auto[1]

from_1to0

auto[1]

auto[0]

38

1

T26

2

T361

1

T97

2

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T16

2

T86

1

T155

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T26

1

T461

1

T373

2

auto[1]

from_0to1

auto[0]

auto[1]

46

1

T99

1

T104

1

T97

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T16

2

T155

1

T361

1

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T16

1

T86

2

T99

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

644

1

T16

8

T26

11

T86

8

auto[1]

643

1

T16

12

T26

9

T86

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

305

1

T16

6

T26

4

T86

7

from_0to1

292

1

T16

5

T26

4

T86

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

656

1

T16

11

T26

10

T86

12

auto[1]

631

1

T16

9

T26

10

T86

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

639

1

T16

9

T26

6

T86

10

auto[1]

648

1

T16

11

T26

14

T86

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T86

2

T99

3

T155

2

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T26

1

T86

1

T104

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T16

1

T104

1

T361

1

auto[0]

from_1to0

auto[1]

auto[1]

35

1

T26

2

T104

1

T97

1

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T86

1

T155

1

T104

1

auto[0]

from_0to1

auto[0]

auto[1]

32

1

T26

1

T86

1

T104

1

auto[0]

from_0to1

auto[1]

auto[0]

32

1

T26

1

T86

1

T361

2

auto[0]

from_0to1

auto[1]

auto[1]

29

1

T99

1

T155

1

T97

1

auto[1]

from_1to0

auto[0]

auto[0]

33

1

T16

1

T86

1

T97

1

auto[1]

from_1to0

auto[0]

auto[1]

32

1

T361

1

T97

1

T461

1

auto[1]

from_1to0

auto[1]

auto[0]

34

1

T16

2

T26

1

T86

2

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T16

2

T86

1

T97

1

auto[1]

from_0to1

auto[0]

auto[0]

43

1

T16

3

T86

1

T155

1

auto[1]

from_0to1

auto[0]

auto[1]

33

1

T16

1

T86

1

T99

1

auto[1]

from_0to1

auto[1]

auto[0]

48

1

T86

1

T155

1

T361

2

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T16

1

T26

2

T86

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

641

1

T16

6

T26

10

T86

10

auto[1]

646

1

T16

14

T26

10

T86

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

317

1

T16

7

T26

5

T86

6

from_0to1

304

1

T16

6

T26

4

T86

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

638

1

T16

11

T26

12

T86

12

auto[1]

649

1

T16

9

T26

8

T86

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

636

1

T16

11

T26

7

T86

10

auto[1]

651

1

T16

9

T26

13

T86

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

27

1

T16

1

T26

1

T86

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T16

1

T99

1

T97

2

auto[0]

from_1to0

auto[1]

auto[0]

41

1

T16

1

T86

1

T99

1

auto[0]

from_1to0

auto[1]

auto[1]

36

1

T104

1

T97

1

T367

2

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T16

1

T86

1

T104

2

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T16

1

T26

1

T99

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T26

1

T99

1

T361

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T86

1

T155

1

T97

1

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T16

1

T86

3

T155

1

auto[1]

from_1to0

auto[0]

auto[1]

34

1

T16

2

T26

2

T99

1

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T16

1

T26

1

T99

1

auto[1]

from_1to0

auto[1]

auto[1]

41

1

T26

1

T86

1

T155

2

auto[1]

from_0to1

auto[0]

auto[0]

33

1

T16

1

T26

1

T86

2

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T16

1

T104

2

T361

1

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T16

1

T99

1

T155

2

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T16

1

T26

1

T86

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

653

1

T16

15

T26

7

T86

11

auto[1]

634

1

T16

5

T26

13

T86

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

300

1

T16

4

T26

4

T86

5

from_0to1

308

1

T16

4

T26

3

T86

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

683

1

T16

10

T26

8

T86

9

auto[1]

604

1

T16

10

T26

12

T86

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645

1

T16

4

T26

9

T86

7

auto[1]

642

1

T16

16

T26

11

T86

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T99

1

T461

2

T367

1

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T16

1

T26

1

T99

1

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T86

1

T155

1

T97

2

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T16

1

T86

2

T99

2

auto[0]

from_0to1

auto[0]

auto[0]

32

1

T16

1

T155

1

T361

2

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T16

1

T86

2

T155

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T86

1

T99

1

T97

2

auto[0]

from_0to1

auto[1]

auto[1]

37

1

T16

1

T86

1

T104

2

auto[1]

from_1to0

auto[0]

auto[0]

28

1

T361

1

T97

3

T368

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T16

2

T26

1

T155

1

auto[1]

from_1to0

auto[1]

auto[0]

38

1

T26

1

T86

1

T104

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T26

1

T86

1

T155

2

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T26

1

T99

1

T361

1

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T26

1

T99

1

T461

1

auto[1]

from_0to1

auto[1]

auto[0]

27

1

T16

1

T155

1

T361

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T26

1

T86

1

T99

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659

1

T16

9

T26

10

T86

11

auto[1]

628

1

T16

11

T26

10

T86

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

301

1

T16

5

T26

6

T86

3

from_0to1

310

1

T16

5

T26

7

T86

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

658

1

T16

9

T26

9

T86

12

auto[1]

629

1

T16

11

T26

11

T86

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T16

12

T26

15

T86

10

auto[1]

640

1

T16

8

T26

5

T86

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

34

1

T16

1

T26

1

T99

2

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T99

1

T155

1

T97

3

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T26

2

T461

1

T373

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T16

1

T86

1

T99

1

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T26

2

T99

1

T155

1

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T16

1

T99

2

T155

1

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T16

1

T26

1

T155

2

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T86

1

T97

1

T373

1

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T16

2

T86

2

T99

1

auto[1]

from_1to0

auto[0]

auto[1]

31

1

T26

1

T104

1

T361

1

auto[1]

from_1to0

auto[1]

auto[0]

36

1

T16

1

T26

1

T361

2

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T26

1

T99

1

T155

1

auto[1]

from_0to1

auto[0]

auto[0]

42

1

T16

2

T26

2

T99

3

auto[1]

from_0to1

auto[0]

auto[1]

34

1

T26

1

T86

1

T99

1

auto[1]

from_0to1

auto[1]

auto[0]

38

1

T26

1

T86

1

T97

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T16

1

T104

1

T97

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

658

1

T16

11

T26

12

T86

13

auto[1]

629

1

T16

9

T26

8

T86

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

295

1

T16

3

T26

5

T86

4

from_0to1

297

1

T16

3

T26

5

T86

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

663

1

T16

8

T26

8

T86

9

auto[1]

624

1

T16

12

T26

12

T86

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

642

1

T16

8

T26

12

T86

10

auto[1]

645

1

T16

12

T26

8

T86

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

30

1

T155

1

T104

1

T461

2

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T16

1

T86

1

T99

2

auto[0]

from_1to0

auto[1]

auto[0]

31

1

T16

1

T26

1

T99

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T16

1

T26

1

T86

1

auto[0]

from_0to1

auto[0]

auto[0]

31

1

T16

1

T26

1

T86

1

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T26

1

T86

1

T97

2

auto[0]

from_0to1

auto[1]

auto[0]

30

1

T26

1

T99

2

T97

2

auto[0]

from_0to1

auto[1]

auto[1]

41

1

T16

1

T155

1

T104

1

auto[1]

from_1to0

auto[0]

auto[0]

36

1

T26

1

T86

1

T104

2

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T26

1

T361

1

T97

5

auto[1]

from_1to0

auto[1]

auto[0]

35

1

T26

1

T86

1

T361

1

auto[1]

from_1to0

auto[1]

auto[1]

29

1

T97

3

T368

2

T462

2

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T16

1

T155

1

T104

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T86

1

T155

1

T104

1

auto[1]

from_0to1

auto[1]

auto[0]

39

1

T26

1

T99

1

T104

2

auto[1]

from_0to1

auto[1]

auto[1]

26

1

T26

1

T86

1

T367

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

628

1

T16

8

T26

8

T86

10

auto[1]

659

1

T16

12

T26

12

T86

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

309

1

T16

7

T26

6

T86

4

from_0to1

307

1

T16

7

T26

5

T86

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

640

1

T16

6

T26

11

T86

9

auto[1]

647

1

T16

14

T26

9

T86

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623

1

T16

11

T26

13

T86

7

auto[1]

664

1

T16

9

T26

7

T86

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T26

1

T361

1

T97

1

auto[0]

from_1to0

auto[0]

auto[1]

32

1

T97

1

T461

1

T462

1

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T16

1

T86

1

T99

3

auto[0]

from_1to0

auto[1]

auto[1]

41

1

T16

2

T26

1

T86

1

auto[0]

from_0to1

auto[0]

auto[0]

31

1

T26

1

T99

2

T155

1

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T26

1

T86

1

T104

1

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T16

2

T26

1

T99

1

auto[0]

from_0to1

auto[1]

auto[1]

34

1

T16

1

T86

1

T361

1

auto[1]

from_1to0

auto[0]

auto[0]

33

1

T26

1

T155

1

T104

1

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T16

1

T26

2

T86

1

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T16

2

T26

1

T155

1

auto[1]

from_1to0

auto[1]

auto[1]

45

1

T16

1

T86

1

T155

1

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T16

1

T26

2

T104

1

auto[1]

from_0to1

auto[0]

auto[1]

37

1

T16

1

T86

1

T104

1

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T16

2

T86

1

T99

1

auto[1]

from_0to1

auto[1]

auto[1]

45

1

T155

3

T97

2

T373

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

635

1

T16

11

T26

8

T86

8

auto[1]

652

1

T16

9

T26

12

T86

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

321

1

T16

4

T26

5

T86

5

from_0to1

317

1

T16

4

T26

4

T86

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

682

1

T16

7

T26

11

T86

11

auto[1]

605

1

T16

13

T26

9

T86

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

659

1

T16

9

T26

7

T86

8

auto[1]

628

1

T16

11

T26

13

T86

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T16

2

T86

1

T99

1

auto[0]

from_1to0

auto[0]

auto[1]

31

1

T99

2

T155

1

T373

1

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T26

1

T104

1

T461

2

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T16

1

T99

1

T361

3

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T99

1

T104

1

T97

1

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T16

1

T26

1

T155

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T16

1

T26

1

T86

1

auto[0]

from_0to1

auto[1]

auto[1]

29

1

T16

1

T361

1

T97

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T26

1

T155

1

T97

1

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T26

2

T86

1

T155

1

auto[1]

from_1to0

auto[1]

auto[0]

33

1

T26

1

T104

2

T97

2

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T16

1

T86

3

T99

1

auto[1]

from_0to1

auto[0]

auto[0]

40

1

T97

1

T367

2

T200

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T16

1

T86

1

T99

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T26

1

T155

1

T104

1

auto[1]

from_0to1

auto[1]

auto[1]

34

1

T26

1

T86

2

T99

2