Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	143337	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

110951

1

T4

25

T5

24

T1

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132908	1			T4	43		T5	22		T1	4
values[0x0]	60197	1			T5	15		T1	6		T2	3
values[0x1]	61183	1			T5	8		T1	1		T2	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	115599	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

138689

1

T4

29

T5

30

T1

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	969	1			T16	4		T192	9		T101	6
valid_sources[0x01]	1857	1			T16	1		T26	1		T82	1
valid_sources[0x02]	981	1			T27	19		T92	1		T101	3
valid_sources[0x03]	684	1			T5	9		T16	1		T70	2
valid_sources[0x04]	695	1			T101	2		T106	2		T90	1
valid_sources[0x05]	771	1			T26	1		T86	1		T61	1
valid_sources[0x06]	703	1			T192	4		T101	1		T97	2
valid_sources[0x07]	803	1			T16	3		T87	1		T28	1
valid_sources[0x08]	1859	1			T26	1		T7	1		T92	2
valid_sources[0x09]	818	1			T16	1		T192	3		T101	1
valid_sources[0x0a]	1434	1			T100	1		T18	1		T155	1
valid_sources[0x0b]	984	1			T7	1		T25	2		T86	2
valid_sources[0x0c]	936	1			T69	1		T7	1		T192	3
valid_sources[0x0d]	1019	1			T86	2		T155	2		T234	1
valid_sources[0x0e]	699	1			T16	1		T101	1		T234	3
valid_sources[0x0f]	671	1			T16	3		T7	1		T86	1
valid_sources[0x10]	786	1			T70	2		T100	2		T31	2
valid_sources[0x11]	930	1			T155	2		T156	50		T31	5
valid_sources[0x12]	867	1			T69	1		T70	2		T86	1
valid_sources[0x13]	650	1			T82	1		T29	1		T192	1
valid_sources[0x14]	746	1			T192	1		T101	2		T31	1
valid_sources[0x15]	857	1			T70	1		T463	1		T31	2
valid_sources[0x16]	855	1			T192	1		T93	1		T155	1
valid_sources[0x17]	1486	1			T5	1		T192	3		T93	2
valid_sources[0x18]	1160	1			T82	1		T12	1		T155	1
valid_sources[0x19]	740	1			T193	1		T156	4		T31	4
valid_sources[0x1a]	932	1			T16	1		T27	20		T86	2
valid_sources[0x1b]	1818	1			T26	1		T47	20		T101	1
valid_sources[0x1c]	1230	1			T16	1		T7	1		T192	1
valid_sources[0x1d]	1003	1			T16	1		T92	1		T60	5
valid_sources[0x1e]	1045	1			T86	1		T101	1		T31	4
valid_sources[0x1f]	788	1			T101	2		T155	1		T234	1
valid_sources[0x20]	909	1			T16	1		T101	12		T156	2
valid_sources[0x21]	759	1			T16	1		T86	1		T31	1
valid_sources[0x22]	723	1			T16	2		T26	2		T192	4
valid_sources[0x23]	935	1			T29	2		T155	1		T156	20
valid_sources[0x24]	636	1			T16	1		T7	1		T101	1
valid_sources[0x25]	870	1			T70	2		T10	1		T155	1
valid_sources[0x26]	959	1			T70	2		T100	2		T155	3
valid_sources[0x27]	811	1			T16	1		T86	1		T87	1
valid_sources[0x28]	864	1			T10	1		T86	2		T155	1
valid_sources[0x29]	1070	1			T86	1		T101	1		T31	1
valid_sources[0x2a]	1017	1			T191	1		T101	1		T104	1
valid_sources[0x2b]	851	1			T2	1		T86	2		T101	1
valid_sources[0x2c]	802	1			T17	1		T7	1		T101	3
valid_sources[0x2d]	931	1			T86	1		T92	1		T193	1
valid_sources[0x2e]	1312	1			T3	1		T72	1		T100	2
valid_sources[0x2f]	803	1			T86	2		T155	1		T31	1
valid_sources[0x30]	833	1			T13	13		T26	3		T101	1
valid_sources[0x31]	1936	1			T16	2		T192	8		T101	2
valid_sources[0x32]	1048	1			T155	1		T106	1		T97	3
valid_sources[0x33]	1371	1			T3	1		T26	1		T31	1
valid_sources[0x34]	809	1			T155	1		T31	2		T104	1
valid_sources[0x35]	701	1			T92	1		T100	5		T101	1
valid_sources[0x36]	983	1			T26	8		T25	2		T192	6
valid_sources[0x37]	743	1			T26	1		T86	1		T191	1
valid_sources[0x38]	795	1			T16	1		T27	1		T70	3
valid_sources[0x39]	915	1			T16	1		T28	1		T192	1
valid_sources[0x3a]	687	1			T2	1		T16	1		T25	1
valid_sources[0x3b]	742	1			T16	1		T26	1		T192	1
valid_sources[0x3c]	1027	1			T70	3		T85	1		T28	1
valid_sources[0x3d]	1882	1			T3	1		T7	1		T92	1
valid_sources[0x3e]	1152	1			T86	1		T30	18		T193	1
valid_sources[0x3f]	1070	1			T7	1		T86	1		T101	2
valid_sources[0x40]	889	1			T86	1		T101	1		T31	1
valid_sources[0x41]	731	1			T26	1		T7	1		T86	1
valid_sources[0x42]	1639	1			T2	2		T193	1		T155	2
valid_sources[0x43]	859	1			T17	2		T26	1		T192	1
valid_sources[0x44]	739	1			T16	3		T86	1		T28	1
valid_sources[0x45]	1554	1			T17	1		T26	2		T86	3
valid_sources[0x46]	606	1			T16	1		T27	6		T86	2
valid_sources[0x47]	799	1			T86	1		T101	3		T104	1
valid_sources[0x48]	891	1			T26	4		T106	1		T91	5
valid_sources[0x49]	860	1			T192	7		T101	1		T31	1
valid_sources[0x4a]	995	1			T100	1		T31	4		T89	1
valid_sources[0x4b]	1316	1			T2	3		T16	7		T70	4
valid_sources[0x4c]	1094	1			T87	1		T31	4		T104	1
valid_sources[0x4d]	815	1			T10	1		T85	29		T92	1
valid_sources[0x4e]	736	1			T7	1		T93	1		T101	5
valid_sources[0x4f]	618	1			T16	6		T27	6		T70	2
valid_sources[0x50]	762	1			T26	7		T192	8		T31	2
valid_sources[0x51]	815	1			T5	2		T193	1		T101	1
valid_sources[0x52]	673	1			T10	1		T28	1		T155	1
valid_sources[0x53]	871	1			T192	4		T104	3		T106	3
valid_sources[0x54]	971	1			T27	5		T70	1		T86	1
valid_sources[0x55]	753	1			T86	1		T61	2		T100	2
valid_sources[0x56]	2704	1			T155	3		T31	2		T106	2
valid_sources[0x57]	1000	1			T86	1		T31	3		T104	1
valid_sources[0x58]	949	1			T86	3		T12	2		T60	3
valid_sources[0x59]	817	1			T26	2		T100	2		T31	1
valid_sources[0x5a]	1081	1			T3	1		T26	2		T82	1
valid_sources[0x5b]	697	1			T31	2		T106	5		T97	3
valid_sources[0x5c]	1625	1			T15	2		T17	1		T31	2
valid_sources[0x5d]	751	1			T26	5		T18	1		T31	3
valid_sources[0x5e]	775	1			T26	2		T155	1		T156	20
valid_sources[0x5f]	710	1			T3	1		T26	1		T192	1
valid_sources[0x60]	769	1			T86	1		T11	13		T192	6
valid_sources[0x61]	841	1			T16	4		T192	2		T31	3
valid_sources[0x62]	895	1			T7	1		T86	1		T92	1
valid_sources[0x63]	751	1			T193	1		T93	1		T234	2
valid_sources[0x64]	694	1			T3	1		T16	2		T70	2
valid_sources[0x65]	736	1			T93	1		T155	1		T31	3
valid_sources[0x66]	849	1			T16	1		T18	5		T101	2
valid_sources[0x67]	903	1			T3	1		T70	4		T192	1
valid_sources[0x68]	646	1			T26	1		T82	1		T86	1
valid_sources[0x69]	1097	1			T2	1		T10	1		T82	1
valid_sources[0x6a]	836	1			T84	10		T86	1		T12	4
valid_sources[0x6b]	958	1			T70	3		T10	1		T86	1
valid_sources[0x6c]	780	1			T93	1		T101	1		T31	1
valid_sources[0x6d]	840	1			T5	4		T16	1		T26	1
valid_sources[0x6e]	970	1			T92	1		T193	1		T31	2
valid_sources[0x6f]	848	1			T7	1		T193	1		T101	2
valid_sources[0x70]	771	1			T29	2		T92	1		T18	1
valid_sources[0x71]	1642	1			T7	1		T101	2		T158	3
valid_sources[0x72]	948	1			T14	45		T25	2		T86	1
valid_sources[0x73]	820	1			T5	1		T26	1		T192	10
valid_sources[0x74]	2235	1			T82	1		T87	2		T93	1
valid_sources[0x75]	640	1			T16	4		T92	1		T155	1
valid_sources[0x76]	1462	1			T16	5		T192	9		T93	1
valid_sources[0x77]	753	1			T93	1		T101	1		T463	1
valid_sources[0x78]	1416	1			T26	7		T86	1		T192	2
valid_sources[0x79]	1024	1			T16	2		T86	2		T92	1
valid_sources[0x7a]	899	1			T26	1		T27	121		T70	2
valid_sources[0x7b]	780	1			T70	1		T86	3		T93	1
valid_sources[0x7c]	737	1			T17	1		T86	1		T191	2
valid_sources[0x7d]	1240	1			T70	3		T18	3		T463	2
valid_sources[0x7e]	803	1			T7	1		T28	1		T192	1
valid_sources[0x7f]	952	1			T7	1		T92	1		T192	10
valid_sources[0x80]	880	1			T26	2		T86	2		T101	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59954

1

T4

25

T5

12

T1

2

values[0x0]

all_enables

biggest_size

29568

1

T5

10

T1

2

T2

2

values[0x1]

all_enables

biggest_size

21429

1

T5

2

T1

1

T13

2