Unified Coverage Report :: Module :: sysrst_ctrl_comboact

Module : sysrst_ctrl_comboact

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_comboact.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act	99.19	100.00	97.56			100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act	99.19	100.00	97.56			100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act	99.19	100.00	97.56			100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act	99.19	100.00	97.56			100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	97.56			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : sysrst_ctrl_comboact

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

33                        logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse;
34         1/1            assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i;
           Tests:       T1 T2 T8 
35         1/1            assign combo_ec_rst_pulse      = cfg_ec_rst_en_i & combo_det_pulse_i;
           Tests:       T1 T2 T8 
36         1/1            assign combo_ot_pulse         = cfg_rst_req_en_i & combo_det_pulse_i;
           Tests:       T1 T2 T8 
37         1/1            assign combo_intr_pulse_o      = cfg_intr_en_i & combo_det_pulse_i;
           Tests:       T1 T2 T8 
38                      
39                        //ec_rst_l_i high->low detection
40                        logic ec_rst_l_det_pulse, ec_rst_l_det_q;
41         1/1            assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q;
           Tests:       T4 T5 T1 
42                      
43                        ////////////////////////////////////
44                        // Bat / OT reset pulse latching //
45                        ////////////////////////////////////
46                      
47                        logic bat_disable_q, bat_disable_d;
48         1/1            assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse;
           Tests:       T58 T40 T43 
49         1/1            assign bat_disable_o = bat_disable_q;
           Tests:       T58 T40 T43 
50                      
51                        logic rst_req_q, rst_req_d;
52         1/1            assign rst_req_d = rst_req_q | combo_ot_pulse;
           Tests:       T33 T42 T58 
53         1/1            assign rst_req_o = rst_req_q;
           Tests:       T33 T42 T58 
54                      
55                        ////////////////////
56                        // EC reset logic //
57                        ////////////////////
58                      
59                        // OT reset will also reset EC
60                        logic timer_expired;
61                        logic ec_rst_l_q, ec_rst_l_d;
62         1/1            assign ec_rst_l_o = ec_rst_l_q;
           Tests:       T1 T2 T8 
63         1/1            assign ec_rst_l_d = (combo_ec_rst_pulse ||
           Tests:       T4 T5 T1 
64                                             ec_rst_l_det_pulse) ? 1'b0 :
65                                            (timer_expired)      ? 1'b1 : ec_rst_l_q;
66                      
67                      
68                        // Reset stretching counter
69                        logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
70         1/1            assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
           Tests:       T4 T5 T1 
71         1/1            assign timer_cnt_d = (timer_expired)       ? '0                 :
           Tests:       T4 T5 T1 
72                                             (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
73                      
74                        ///////////////
75                        // Registers //
76                        ///////////////
77                      
78                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
79         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
80         1/1                bat_disable_q  <= 1'b0;
           Tests:       T4 T5 T1 
81         1/1                ec_rst_l_det_q <= 1'b1;  // active low signal
           Tests:       T4 T5 T1 
82         1/1                rst_req_q      <= 1'b0;
           Tests:       T4 T5 T1 
83         1/1                ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
           Tests:       T4 T5 T1 
84         1/1                timer_cnt_q    <= '0;
           Tests:       T4 T5 T1 
85                          end else begin
86         1/1                bat_disable_q  <= bat_disable_d;
           Tests:       T4 T5 T1 
87         1/1                ec_rst_l_det_q <= ec_rst_l_i;
           Tests:       T4 T5 T1 
88         1/1                rst_req_q      <= rst_req_d;
           Tests:       T4 T5 T1 
89         1/1                ec_rst_l_q     <= ec_rst_l_d;
           Tests:       T4 T5 T1 
90         1/1                timer_cnt_q    <= timer_cnt_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Module : sysrst_ctrl_comboact

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T31,T32,T33
1	1	Covered	T58,T40,T43

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T42,T58,T40
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T31,T32,T33
1	1	Covered	T33,T42,T58

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T33,T58
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T58,T40,T43
1	0	Covered	T58,T40,T43

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T33,T42,T58
1	0	Covered	T33,T42,T58

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T8

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T8

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

---

Branch Coverage for Module : sysrst_ctrl_comboact

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

63           assign ec_rst_l_d = (combo_ec_rst_pulse ||
                                                       
64                                ec_rst_l_det_pulse) ? 1'b0 :
                                                      -1-  
                                                      ==>  
65                               (timer_expired)      ? 1'b1 : ec_rst_l_q;
                                                      -2-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T1,T2,T8
0	0	Covered	T4,T5,T1

71           assign timer_cnt_d = (timer_expired)       ? '0                 :
                                                        -1-  
                                                        ==>  
72                                (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
                                                        -2-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T8
0	1	Covered	T4,T5,T1
0	0	Covered	T1,T2,T8

79             if (!rst_ni) begin
               -1-  
80               bat_disable_q  <= 1'b0;
                 ==>
81               ec_rst_l_det_q <= 1'b1;  // active low signal
82               rst_req_q      <= 1'b0;
83               ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
84               timer_cnt_q    <= '0;
85             end else begin
86               bat_disable_q  <= bat_disable_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

33                        logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse;
34         1/1            assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i;
           Tests:       T1 T2 T8 
35         1/1            assign combo_ec_rst_pulse      = cfg_ec_rst_en_i & combo_det_pulse_i;
           Tests:       T1 T2 T8 
36         1/1            assign combo_ot_pulse         = cfg_rst_req_en_i & combo_det_pulse_i;
           Tests:       T1 T2 T8 
37         1/1            assign combo_intr_pulse_o      = cfg_intr_en_i & combo_det_pulse_i;
           Tests:       T1 T2 T8 
38                      
39                        //ec_rst_l_i high->low detection
40                        logic ec_rst_l_det_pulse, ec_rst_l_det_q;
41         1/1            assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q;
           Tests:       T4 T5 T1 
42                      
43                        ////////////////////////////////////
44                        // Bat / OT reset pulse latching //
45                        ////////////////////////////////////
46                      
47                        logic bat_disable_q, bat_disable_d;
48         1/1            assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse;
           Tests:       T40 T43 T44 
49         1/1            assign bat_disable_o = bat_disable_q;
           Tests:       T40 T43 T44 
50                      
51                        logic rst_req_q, rst_req_d;
52         1/1            assign rst_req_d = rst_req_q | combo_ot_pulse;
           Tests:       T41 T307 T114 
53         1/1            assign rst_req_o = rst_req_q;
           Tests:       T41 T307 T114 
54                      
55                        ////////////////////
56                        // EC reset logic //
57                        ////////////////////
58                      
59                        // OT reset will also reset EC
60                        logic timer_expired;
61                        logic ec_rst_l_q, ec_rst_l_d;
62         1/1            assign ec_rst_l_o = ec_rst_l_q;
           Tests:       T1 T2 T8 
63         1/1            assign ec_rst_l_d = (combo_ec_rst_pulse ||
           Tests:       T4 T5 T1 
64                                             ec_rst_l_det_pulse) ? 1'b0 :
65                                            (timer_expired)      ? 1'b1 : ec_rst_l_q;
66                      
67                      
68                        // Reset stretching counter
69                        logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
70         1/1            assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
           Tests:       T4 T5 T1 
71         1/1            assign timer_cnt_d = (timer_expired)       ? '0                 :
           Tests:       T4 T5 T1 
72                                             (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
73                      
74                        ///////////////
75                        // Registers //
76                        ///////////////
77                      
78                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
79         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
80         1/1                bat_disable_q  <= 1'b0;
           Tests:       T4 T5 T1 
81         1/1                ec_rst_l_det_q <= 1'b1;  // active low signal
           Tests:       T4 T5 T1 
82         1/1                rst_req_q      <= 1'b0;
           Tests:       T4 T5 T1 
83         1/1                ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
           Tests:       T4 T5 T1 
84         1/1                timer_cnt_q    <= '0;
           Tests:       T4 T5 T1 
85                          end else begin
86         1/1                bat_disable_q  <= bat_disable_d;
           Tests:       T4 T5 T1 
87         1/1                ec_rst_l_det_q <= ec_rst_l_i;
           Tests:       T4 T5 T1 
88         1/1                rst_req_q      <= rst_req_d;
           Tests:       T4 T5 T1 
89         1/1                ec_rst_l_q     <= ec_rst_l_d;
           Tests:       T4 T5 T1 
90         1/1                timer_cnt_q    <= timer_cnt_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T31,T32,T58
1	1	Covered	T40,T43,T44

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T41,T307,T325
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T42,T41,T123
1	1	Covered	T41,T307,T114

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T33,T76
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T40,T43,T44
1	0	Covered	T40,T43,T44

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T41,T307,T114
1	0	Covered	T41,T307,T114

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T8

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T8

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

63           assign ec_rst_l_d = (combo_ec_rst_pulse ||
                                                       
64                                ec_rst_l_det_pulse) ? 1'b0 :
                                                      -1-  
                                                      ==>  
65                               (timer_expired)      ? 1'b1 : ec_rst_l_q;
                                                      -2-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T1,T2,T8
0	0	Covered	T4,T5,T1

71           assign timer_cnt_d = (timer_expired)       ? '0                 :
                                                        -1-  
                                                        ==>  
72                                (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
                                                        -2-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T8
0	1	Covered	T4,T5,T1
0	0	Covered	T1,T2,T8

79             if (!rst_ni) begin
               -1-  
80               bat_disable_q  <= 1'b0;
                 ==>
81               ec_rst_l_det_q <= 1'b1;  // active low signal
82               rst_req_q      <= 1'b0;
83               ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
84               timer_cnt_q    <= '0;
85             end else begin
86               bat_disable_q  <= bat_disable_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

33                        logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse;
34         1/1            assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i;
           Tests:       T20 T32 T33 
35         1/1            assign combo_ec_rst_pulse      = cfg_ec_rst_en_i & combo_det_pulse_i;
           Tests:       T31 T20 T32 
36         1/1            assign combo_ot_pulse         = cfg_rst_req_en_i & combo_det_pulse_i;
           Tests:       T31 T20 T33 
37         1/1            assign combo_intr_pulse_o      = cfg_intr_en_i & combo_det_pulse_i;
           Tests:       T31 T20 T32 
38                      
39                        //ec_rst_l_i high->low detection
40                        logic ec_rst_l_det_pulse, ec_rst_l_det_q;
41         1/1            assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q;
           Tests:       T4 T5 T1 
42                      
43                        ////////////////////////////////////
44                        // Bat / OT reset pulse latching //
45                        ////////////////////////////////////
46                      
47                        logic bat_disable_q, bat_disable_d;
48         1/1            assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse;
           Tests:       T43 T41 T142 
49         1/1            assign bat_disable_o = bat_disable_q;
           Tests:       T43 T41 T142 
50                      
51                        logic rst_req_q, rst_req_d;
52         1/1            assign rst_req_d = rst_req_q | combo_ot_pulse;
           Tests:       T33 T40 T41 
53         1/1            assign rst_req_o = rst_req_q;
           Tests:       T33 T40 T41 
54                      
55                        ////////////////////
56                        // EC reset logic //
57                        ////////////////////
58                      
59                        // OT reset will also reset EC
60                        logic timer_expired;
61                        logic ec_rst_l_q, ec_rst_l_d;
62         1/1            assign ec_rst_l_o = ec_rst_l_q;
           Tests:       T1 T2 T8 
63         1/1            assign ec_rst_l_d = (combo_ec_rst_pulse ||
           Tests:       T4 T5 T1 
64                                             ec_rst_l_det_pulse) ? 1'b0 :
65                                            (timer_expired)      ? 1'b1 : ec_rst_l_q;
66                      
67                      
68                        // Reset stretching counter
69                        logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
70         1/1            assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
           Tests:       T4 T5 T1 
71         1/1            assign timer_cnt_d = (timer_expired)       ? '0                 :
           Tests:       T4 T5 T1 
72                                             (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
73                      
74                        ///////////////
75                        // Registers //
76                        ///////////////
77                      
78                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
79         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
80         1/1                bat_disable_q  <= 1'b0;
           Tests:       T4 T5 T1 
81         1/1                ec_rst_l_det_q <= 1'b1;  // active low signal
           Tests:       T4 T5 T1 
82         1/1                rst_req_q      <= 1'b0;
           Tests:       T4 T5 T1 
83         1/1                ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
           Tests:       T4 T5 T1 
84         1/1                timer_cnt_q    <= '0;
           Tests:       T4 T5 T1 
85                          end else begin
86         1/1                bat_disable_q  <= bat_disable_d;
           Tests:       T4 T5 T1 
87         1/1                ec_rst_l_det_q <= ec_rst_l_i;
           Tests:       T4 T5 T1 
88         1/1                rst_req_q      <= rst_req_d;
           Tests:       T4 T5 T1 
89         1/1                ec_rst_l_q     <= ec_rst_l_d;
           Tests:       T4 T5 T1 
90         1/1                timer_cnt_q    <= timer_cnt_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T33,T40
1	0	Covered	T32,T58,T43
1	1	Covered	T43,T41,T142

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T142,T112,T287
1	0	Covered	T31,T20,T32
1	1	Covered	T20,T33,T40

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T76,T43
1	0	Covered	T31,T33,T58
1	1	Covered	T33,T40,T41

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T76,T43
1	0	Covered	T31,T32,T33
1	1	Covered	T33,T40,T41

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T43,T41,T142
1	0	Covered	T43,T41,T142

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T33,T40,T41
1	0	Covered	T33,T40,T41

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T1
1	0	Covered	T20,T33,T40

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T8

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

63           assign ec_rst_l_d = (combo_ec_rst_pulse ||
                                                       
64                                ec_rst_l_det_pulse) ? 1'b0 :
                                                      -1-  
                                                      ==>  
65                               (timer_expired)      ? 1'b1 : ec_rst_l_q;
                                                      -2-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T1,T2,T8
0	0	Covered	T4,T5,T1

71           assign timer_cnt_d = (timer_expired)       ? '0                 :
                                                        -1-  
                                                        ==>  
72                                (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
                                                        -2-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T8
0	1	Covered	T4,T5,T1
0	0	Covered	T1,T2,T8

79             if (!rst_ni) begin
               -1-  
80               bat_disable_q  <= 1'b0;
                 ==>
81               ec_rst_l_det_q <= 1'b1;  // active low signal
82               rst_req_q      <= 1'b0;
83               ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
84               timer_cnt_q    <= '0;
85             end else begin
86               bat_disable_q  <= bat_disable_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

33                        logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse;
34         1/1            assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i;
           Tests:       T20 T32 T59 
35         1/1            assign combo_ec_rst_pulse      = cfg_ec_rst_en_i & combo_det_pulse_i;
           Tests:       T20 T32 T33 
36         1/1            assign combo_ot_pulse         = cfg_rst_req_en_i & combo_det_pulse_i;
           Tests:       T20 T42 T58 
37         1/1            assign combo_intr_pulse_o      = cfg_intr_en_i & combo_det_pulse_i;
           Tests:       T20 T33 T42 
38                      
39                        //ec_rst_l_i high->low detection
40                        logic ec_rst_l_det_pulse, ec_rst_l_det_q;
41         1/1            assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q;
           Tests:       T4 T5 T1 
42                      
43                        ////////////////////////////////////
44                        // Bat / OT reset pulse latching //
45                        ////////////////////////////////////
46                      
47                        logic bat_disable_q, bat_disable_d;
48         1/1            assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse;
           Tests:       T58 T114 T326 
49         1/1            assign bat_disable_o = bat_disable_q;
           Tests:       T58 T114 T326 
50                      
51                        logic rst_req_q, rst_req_d;
52         1/1            assign rst_req_d = rst_req_q | combo_ot_pulse;
           Tests:       T58 T40 T43 
53         1/1            assign rst_req_o = rst_req_q;
           Tests:       T58 T40 T43 
54                      
55                        ////////////////////
56                        // EC reset logic //
57                        ////////////////////
58                      
59                        // OT reset will also reset EC
60                        logic timer_expired;
61                        logic ec_rst_l_q, ec_rst_l_d;
62         1/1            assign ec_rst_l_o = ec_rst_l_q;
           Tests:       T1 T2 T8 
63         1/1            assign ec_rst_l_d = (combo_ec_rst_pulse ||
           Tests:       T4 T5 T1 
64                                             ec_rst_l_det_pulse) ? 1'b0 :
65                                            (timer_expired)      ? 1'b1 : ec_rst_l_q;
66                      
67                      
68                        // Reset stretching counter
69                        logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
70         1/1            assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
           Tests:       T4 T5 T1 
71         1/1            assign timer_cnt_d = (timer_expired)       ? '0                 :
           Tests:       T4 T5 T1 
72                                             (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
73                      
74                        ///////////////
75                        // Registers //
76                        ///////////////
77                      
78                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
79         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
80         1/1                bat_disable_q  <= 1'b0;
           Tests:       T4 T5 T1 
81         1/1                ec_rst_l_det_q <= 1'b1;  // active low signal
           Tests:       T4 T5 T1 
82         1/1                rst_req_q      <= 1'b0;
           Tests:       T4 T5 T1 
83         1/1                ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
           Tests:       T4 T5 T1 
84         1/1                timer_cnt_q    <= '0;
           Tests:       T4 T5 T1 
85                          end else begin
86         1/1                bat_disable_q  <= bat_disable_d;
           Tests:       T4 T5 T1 
87         1/1                ec_rst_l_det_q <= ec_rst_l_i;
           Tests:       T4 T5 T1 
88         1/1                rst_req_q      <= rst_req_d;
           Tests:       T4 T5 T1 
89         1/1                ec_rst_l_q     <= ec_rst_l_d;
           Tests:       T4 T5 T1 
90         1/1                timer_cnt_q    <= timer_cnt_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T42,T40
1	0	Covered	T32,T59,T58
1	1	Covered	T58,T114,T326

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T42,T58,T40
1	0	Covered	T20,T32,T33
1	1	Covered	T20,T76,T43

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T42,T76
1	0	Covered	T58,T40,T43
1	1	Covered	T58,T40,T43

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T58,T76
1	0	Covered	T33,T42,T40
1	1	Covered	T42,T40,T43

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T58,T114,T326
1	0	Covered	T58,T114,T326

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T58,T40,T43
1	0	Covered	T58,T40,T43

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T1
1	0	Covered	T20,T76,T43

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T8

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

63           assign ec_rst_l_d = (combo_ec_rst_pulse ||
                                                       
64                                ec_rst_l_det_pulse) ? 1'b0 :
                                                      -1-  
                                                      ==>  
65                               (timer_expired)      ? 1'b1 : ec_rst_l_q;
                                                      -2-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T1,T2,T8
0	0	Covered	T4,T5,T1

71           assign timer_cnt_d = (timer_expired)       ? '0                 :
                                                        -1-  
                                                        ==>  
72                                (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
                                                        -2-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T8
0	1	Covered	T4,T5,T1
0	0	Covered	T1,T2,T8

79             if (!rst_ni) begin
               -1-  
80               bat_disable_q  <= 1'b0;
                 ==>
81               ec_rst_l_det_q <= 1'b1;  // active low signal
82               rst_req_q      <= 1'b0;
83               ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
84               timer_cnt_q    <= '0;
85             end else begin
86               bat_disable_q  <= bat_disable_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	79	11	11	100.00

33                        logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse;
34         1/1            assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i;
           Tests:       T20 T32 T33 
35         1/1            assign combo_ec_rst_pulse      = cfg_ec_rst_en_i & combo_det_pulse_i;
           Tests:       T31 T20 T33 
36         1/1            assign combo_ot_pulse         = cfg_rst_req_en_i & combo_det_pulse_i;
           Tests:       T31 T20 T32 
37         1/1            assign combo_intr_pulse_o      = cfg_intr_en_i & combo_det_pulse_i;
           Tests:       T20 T32 T59 
38                      
39                        //ec_rst_l_i high->low detection
40                        logic ec_rst_l_det_pulse, ec_rst_l_det_q;
41         1/1            assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q;
           Tests:       T4 T5 T1 
42                      
43                        ////////////////////////////////////
44                        // Bat / OT reset pulse latching //
45                        ////////////////////////////////////
46                      
47                        logic bat_disable_q, bat_disable_d;
48         1/1            assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse;
           Tests:       T40 T41 T142 
49         1/1            assign bat_disable_o = bat_disable_q;
           Tests:       T40 T41 T142 
50                      
51                        logic rst_req_q, rst_req_d;
52         1/1            assign rst_req_d = rst_req_q | combo_ot_pulse;
           Tests:       T42 T41 T44 
53         1/1            assign rst_req_o = rst_req_q;
           Tests:       T42 T41 T44 
54                      
55                        ////////////////////
56                        // EC reset logic //
57                        ////////////////////
58                      
59                        // OT reset will also reset EC
60                        logic timer_expired;
61                        logic ec_rst_l_q, ec_rst_l_d;
62         1/1            assign ec_rst_l_o = ec_rst_l_q;
           Tests:       T1 T2 T8 
63         1/1            assign ec_rst_l_d = (combo_ec_rst_pulse ||
           Tests:       T4 T5 T1 
64                                             ec_rst_l_det_pulse) ? 1'b0 :
65                                            (timer_expired)      ? 1'b1 : ec_rst_l_q;
66                      
67                      
68                        // Reset stretching counter
69                        logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
70         1/1            assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q);
           Tests:       T4 T5 T1 
71         1/1            assign timer_cnt_d = (timer_expired)       ? '0                 :
           Tests:       T4 T5 T1 
72                                             (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
73                      
74                        ///////////////
75                        // Registers //
76                        ///////////////
77                      
78                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
79         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
80         1/1                bat_disable_q  <= 1'b0;
           Tests:       T4 T5 T1 
81         1/1                ec_rst_l_det_q <= 1'b1;  // active low signal
           Tests:       T4 T5 T1 
82         1/1                rst_req_q      <= 1'b0;
           Tests:       T4 T5 T1 
83         1/1                ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
           Tests:       T4 T5 T1 
84         1/1                timer_cnt_q    <= '0;
           Tests:       T4 T5 T1 
85                          end else begin
86         1/1                bat_disable_q  <= bat_disable_d;
           Tests:       T4 T5 T1 
87         1/1                ec_rst_l_det_q <= ec_rst_l_i;
           Tests:       T4 T5 T1 
88         1/1                rst_req_q      <= rst_req_d;
           Tests:       T4 T5 T1 
89         1/1                ec_rst_l_q     <= ec_rst_l_d;
           Tests:       T4 T5 T1 
90         1/1                timer_cnt_q    <= timer_cnt_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

	Total	Covered	Percent
Conditions	41	40	97.56
Logical	41	40	97.56
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T42,T58
1	0	Covered	T32,T33,T40
1	1	Covered	T40,T41,T142

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T42,T125,T326
1	0	Covered	T31,T20,T33
1	1	Covered	T20,T58,T40

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T58,T40
1	0	Covered	T31,T32,T33
1	1	Covered	T42,T41,T44

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T20,T42,T58
1	0	Covered	T32,T59,T43
1	1	Covered	T44,T45,T46

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T40,T41,T142
1	0	Covered	T40,T41,T142

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T42,T41,T44
1	0	Covered	T42,T41,T44

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T1
1	0	Covered	T20,T58,T40

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T8

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T8

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	63	3	3	100.00
TERNARY	71	3	3	100.00
IF	79	2	2	100.00

63           assign ec_rst_l_d = (combo_ec_rst_pulse ||
                                                       
64                                ec_rst_l_det_pulse) ? 1'b0 :
                                                      -1-  
                                                      ==>  
65                               (timer_expired)      ? 1'b1 : ec_rst_l_q;
                                                      -2-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T1,T2,T8
0	0	Covered	T4,T5,T1

71           assign timer_cnt_d = (timer_expired)       ? '0                 :
                                                        -1-  
                                                        ==>  
72                                (ec_rst_l_q == 1'b0)  ? timer_cnt_q + 1'b1 : timer_cnt_q;
                                                        -2-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T8
0	1	Covered	T4,T5,T1
0	0	Covered	T1,T2,T8

79             if (!rst_ni) begin
               -1-  
80               bat_disable_q  <= 1'b0;
                 ==>
81               ec_rst_l_det_q <= 1'b1;  // active low signal
82               rst_req_q      <= 1'b0;
83               ec_rst_l_q     <= 1'b0;  // asserted when power-on-reset is asserted
84               timer_cnt_q    <= '0;
85             end else begin
86               bat_disable_q  <= bat_disable_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1