| T502 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.3902563258 |
|
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Sep 09 07:11:13 AM UTC 24 |
Sep 09 07:11:40 AM UTC 24 |
6792076636 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.3566008862 |
|
|
Sep 09 07:11:28 AM UTC 24 |
Sep 09 07:11:41 AM UTC 24 |
2509842360 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1490883712 |
|
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Sep 09 07:11:34 AM UTC 24 |
Sep 09 07:11:42 AM UTC 24 |
4718723139 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.227612841 |
|
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Sep 09 07:11:34 AM UTC 24 |
Sep 09 07:11:43 AM UTC 24 |
2613718789 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.56823751 |
|
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Sep 09 07:11:38 AM UTC 24 |
Sep 09 07:11:43 AM UTC 24 |
2523507911 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.2907629017 |
|
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Sep 09 07:11:40 AM UTC 24 |
Sep 09 07:11:43 AM UTC 24 |
5105464107 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3020092277 |
|
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Sep 09 07:11:36 AM UTC 24 |
Sep 09 07:11:44 AM UTC 24 |
11043810333 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1243099018 |
|
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Sep 09 07:11:39 AM UTC 24 |
Sep 09 07:11:45 AM UTC 24 |
3597682683 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.3385453343 |
|
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Sep 09 07:11:40 AM UTC 24 |
Sep 09 07:11:45 AM UTC 24 |
3670026372 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2201293290 |
|
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Sep 09 07:11:34 AM UTC 24 |
Sep 09 07:11:46 AM UTC 24 |
4429166977 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.4198780536 |
|
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Sep 09 07:11:27 AM UTC 24 |
Sep 09 07:11:46 AM UTC 24 |
14851978730 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.2486778986 |
|
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Sep 09 07:11:44 AM UTC 24 |
Sep 09 07:11:46 AM UTC 24 |
2195517069 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.3480511134 |
|
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Sep 09 07:11:36 AM UTC 24 |
Sep 09 07:11:47 AM UTC 24 |
2012718562 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.1890360694 |
|
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Sep 09 07:09:54 AM UTC 24 |
Sep 09 07:12:08 AM UTC 24 |
150630356729 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3602326575 |
|
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Sep 09 07:11:38 AM UTC 24 |
Sep 09 07:11:48 AM UTC 24 |
2614951634 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1549027660 |
|
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Sep 09 07:10:25 AM UTC 24 |
Sep 09 07:11:49 AM UTC 24 |
121208220745 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.4082699313 |
|
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Sep 09 07:11:46 AM UTC 24 |
Sep 09 07:11:49 AM UTC 24 |
2546951745 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1758188686 |
|
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Sep 09 07:11:46 AM UTC 24 |
Sep 09 07:11:51 AM UTC 24 |
2622351814 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1539367859 |
|
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Sep 09 07:11:34 AM UTC 24 |
Sep 09 07:11:53 AM UTC 24 |
5933299690 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2194517190 |
|
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Sep 09 07:10:04 AM UTC 24 |
Sep 09 07:11:53 AM UTC 24 |
407174945327 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.2471000753 |
|
|
Sep 09 07:11:45 AM UTC 24 |
Sep 09 07:11:54 AM UTC 24 |
2216474966 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.295600668 |
|
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Sep 09 07:11:47 AM UTC 24 |
Sep 09 07:11:54 AM UTC 24 |
4623417216 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.1969977735 |
|
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Sep 09 07:11:50 AM UTC 24 |
Sep 09 07:11:55 AM UTC 24 |
2690293224 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1000787952 |
|
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Sep 09 07:11:27 AM UTC 24 |
Sep 09 07:11:55 AM UTC 24 |
29800766530 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.338800531 |
|
|
Sep 09 07:11:44 AM UTC 24 |
Sep 09 07:11:56 AM UTC 24 |
2012203267 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3802053696 |
|
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Sep 09 07:11:47 AM UTC 24 |
Sep 09 07:11:57 AM UTC 24 |
3350978757 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.1796062171 |
|
|
Sep 09 07:11:54 AM UTC 24 |
Sep 09 07:11:58 AM UTC 24 |
2043124220 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1105514857 |
|
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Sep 09 07:11:39 AM UTC 24 |
Sep 09 07:12:00 AM UTC 24 |
4148016605 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.3142237285 |
|
|
Sep 09 07:12:01 AM UTC 24 |
Sep 09 07:12:07 AM UTC 24 |
3283399516 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.1262447173 |
|
|
Sep 09 07:11:55 AM UTC 24 |
Sep 09 07:12:00 AM UTC 24 |
2204024553 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.600276699 |
|
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Sep 09 07:11:56 AM UTC 24 |
Sep 09 07:12:00 AM UTC 24 |
2525662283 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3931661666 |
|
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Sep 09 07:10:12 AM UTC 24 |
Sep 09 07:12:00 AM UTC 24 |
49982738467 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2910039005 |
|
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Sep 09 07:11:55 AM UTC 24 |
Sep 09 07:12:01 AM UTC 24 |
2125978200 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.3322521090 |
|
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Sep 09 07:11:45 AM UTC 24 |
Sep 09 07:12:01 AM UTC 24 |
2453850586 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1541559002 |
|
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Sep 09 07:11:46 AM UTC 24 |
Sep 09 07:12:01 AM UTC 24 |
3277888691 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3528192915 |
|
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Sep 09 07:11:27 AM UTC 24 |
Sep 09 07:12:02 AM UTC 24 |
9712955812 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1436141868 |
|
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Sep 09 07:09:38 AM UTC 24 |
Sep 09 07:12:03 AM UTC 24 |
209141465627 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1019702520 |
|
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Sep 09 07:11:43 AM UTC 24 |
Sep 09 07:12:03 AM UTC 24 |
7793510643 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3754669193 |
|
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Sep 09 07:11:54 AM UTC 24 |
Sep 09 07:12:04 AM UTC 24 |
11804394622 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.478963625 |
|
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Sep 09 07:11:52 AM UTC 24 |
Sep 09 07:12:07 AM UTC 24 |
7486365992 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.1754222713 |
|
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Sep 09 07:12:03 AM UTC 24 |
Sep 09 07:12:08 AM UTC 24 |
2484585914 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.318681136 |
|
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Sep 09 07:11:55 AM UTC 24 |
Sep 09 07:12:09 AM UTC 24 |
2452548142 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.774448602 |
|
|
Sep 09 07:11:44 AM UTC 24 |
Sep 09 07:12:09 AM UTC 24 |
6224795603 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.4101388641 |
|
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Sep 09 07:12:05 AM UTC 24 |
Sep 09 07:12:10 AM UTC 24 |
2530266786 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.73566906 |
|
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Sep 09 07:11:20 AM UTC 24 |
Sep 09 07:12:11 AM UTC 24 |
36901386272 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3469685165 |
|
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Sep 09 07:11:12 AM UTC 24 |
Sep 09 07:12:11 AM UTC 24 |
1555581389632 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3306061908 |
|
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Sep 09 07:12:05 AM UTC 24 |
Sep 09 07:12:11 AM UTC 24 |
2621198397 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2005059782 |
|
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Sep 09 07:12:01 AM UTC 24 |
Sep 09 07:12:12 AM UTC 24 |
12453881428 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.161509501 |
|
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Sep 09 07:12:08 AM UTC 24 |
Sep 09 07:12:12 AM UTC 24 |
10300396374 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.1701776361 |
|
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Sep 09 07:12:01 AM UTC 24 |
Sep 09 07:12:12 AM UTC 24 |
5301735789 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1624564087 |
|
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Sep 09 07:09:53 AM UTC 24 |
Sep 09 07:12:13 AM UTC 24 |
98636430423 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.2924021096 |
|
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Sep 09 07:12:02 AM UTC 24 |
Sep 09 07:12:13 AM UTC 24 |
2011954151 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.776445550 |
|
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Sep 09 07:12:08 AM UTC 24 |
Sep 09 07:12:14 AM UTC 24 |
3987282895 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1284286605 |
|
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Sep 09 07:12:10 AM UTC 24 |
Sep 09 07:12:16 AM UTC 24 |
4300845994 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.2518746825 |
|
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Sep 09 07:10:47 AM UTC 24 |
Sep 09 07:12:17 AM UTC 24 |
125644710619 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.4077062409 |
|
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Sep 09 07:12:13 AM UTC 24 |
Sep 09 07:12:17 AM UTC 24 |
2639688301 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.4073209958 |
|
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Sep 09 07:12:01 AM UTC 24 |
Sep 09 07:12:17 AM UTC 24 |
31187038444 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.158200690 |
|
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Sep 09 07:11:59 AM UTC 24 |
Sep 09 07:12:18 AM UTC 24 |
3983345575 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.2697843611 |
|
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Sep 09 07:12:11 AM UTC 24 |
Sep 09 07:12:18 AM UTC 24 |
2015410184 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3992997293 |
|
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Sep 09 07:12:13 AM UTC 24 |
Sep 09 07:12:18 AM UTC 24 |
3453278570 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.3907194870 |
|
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Sep 09 07:10:04 AM UTC 24 |
Sep 09 07:12:19 AM UTC 24 |
206520837627 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1571490037 |
|
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Sep 09 07:12:15 AM UTC 24 |
Sep 09 07:12:19 AM UTC 24 |
5512939094 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.2175119235 |
|
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Sep 09 07:12:13 AM UTC 24 |
Sep 09 07:12:20 AM UTC 24 |
2518275439 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3215271700 |
|
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Sep 09 07:12:13 AM UTC 24 |
Sep 09 07:12:21 AM UTC 24 |
2211504729 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.931280546 |
|
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Sep 09 07:12:08 AM UTC 24 |
Sep 09 07:12:22 AM UTC 24 |
3268178929 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.3975574439 |
|
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Sep 09 07:12:13 AM UTC 24 |
Sep 09 07:12:22 AM UTC 24 |
2460191124 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.170555010 |
|
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Sep 09 07:12:15 AM UTC 24 |
Sep 09 07:12:22 AM UTC 24 |
2449608685 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.749295627 |
|
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Sep 09 07:12:11 AM UTC 24 |
Sep 09 07:12:22 AM UTC 24 |
2108799046 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.609391655 |
|
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Sep 09 07:12:20 AM UTC 24 |
Sep 09 07:12:23 AM UTC 24 |
2504036141 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2749752367 |
|
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Sep 09 07:09:38 AM UTC 24 |
Sep 09 07:12:23 AM UTC 24 |
107778187618 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.3759416846 |
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Sep 09 07:12:20 AM UTC 24 |
Sep 09 07:12:23 AM UTC 24 |
2072485645 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3098917296 |
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Sep 09 07:12:17 AM UTC 24 |
Sep 09 07:12:24 AM UTC 24 |
12785442933 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.4222346340 |
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Sep 09 07:12:01 AM UTC 24 |
Sep 09 07:12:24 AM UTC 24 |
33195494711 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.4102023180 |
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Sep 09 07:12:40 AM UTC 24 |
Sep 09 07:12:55 AM UTC 24 |
3986992201 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.2170062764 |
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Sep 09 07:12:20 AM UTC 24 |
Sep 09 07:12:26 AM UTC 24 |
2012281173 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.2193011808 |
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Sep 09 07:12:20 AM UTC 24 |
Sep 09 07:12:28 AM UTC 24 |
2511267266 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2280627434 |
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Sep 09 07:12:20 AM UTC 24 |
Sep 09 07:12:28 AM UTC 24 |
2113142980 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.3847118591 |
|
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Sep 09 07:12:25 AM UTC 24 |
Sep 09 07:12:29 AM UTC 24 |
2494575961 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2225009601 |
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Sep 09 07:12:25 AM UTC 24 |
Sep 09 07:12:29 AM UTC 24 |
2125413814 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.821823140 |
|
|
Sep 09 07:12:20 AM UTC 24 |
Sep 09 07:12:29 AM UTC 24 |
2610889404 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.3720454880 |
|
|
Sep 09 07:12:25 AM UTC 24 |
Sep 09 07:12:30 AM UTC 24 |
2025928539 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2370977490 |
|
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Sep 09 07:10:59 AM UTC 24 |
Sep 09 07:12:31 AM UTC 24 |
32879165726 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.174533040 |
|
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Sep 09 07:09:29 AM UTC 24 |
Sep 09 07:12:32 AM UTC 24 |
126865985277 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1653728508 |
|
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Sep 09 07:12:10 AM UTC 24 |
Sep 09 07:12:32 AM UTC 24 |
5683102845 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.544281983 |
|
|
Sep 09 07:12:25 AM UTC 24 |
Sep 09 07:12:33 AM UTC 24 |
3064613175 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.165778009 |
|
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Sep 09 07:12:28 AM UTC 24 |
Sep 09 07:12:33 AM UTC 24 |
2527805747 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.347229775 |
|
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Sep 09 07:12:28 AM UTC 24 |
Sep 09 07:12:33 AM UTC 24 |
2627006092 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3705153157 |
|
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Sep 09 07:12:25 AM UTC 24 |
Sep 09 07:12:36 AM UTC 24 |
14007801345 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.865769219 |
|
|
Sep 09 07:12:28 AM UTC 24 |
Sep 09 07:12:36 AM UTC 24 |
2065197454 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.2345186472 |
|
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Sep 09 07:11:27 AM UTC 24 |
Sep 09 07:12:37 AM UTC 24 |
80263930499 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1895577891 |
|
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Sep 09 07:12:31 AM UTC 24 |
Sep 09 07:12:38 AM UTC 24 |
3803741276 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2226330436 |
|
|
Sep 09 07:12:54 AM UTC 24 |
Sep 09 07:13:01 AM UTC 24 |
2018158549 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2588631241 |
|
|
Sep 09 07:12:31 AM UTC 24 |
Sep 09 07:12:38 AM UTC 24 |
3481448660 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.1492989224 |
|
|
Sep 09 07:12:34 AM UTC 24 |
Sep 09 07:12:38 AM UTC 24 |
2082336626 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2315124468 |
|
|
Sep 09 07:12:22 AM UTC 24 |
Sep 09 07:12:39 AM UTC 24 |
2675268018 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.3884715972 |
|
|
Sep 09 07:12:33 AM UTC 24 |
Sep 09 07:12:40 AM UTC 24 |
7067152020 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.11174603 |
|
|
Sep 09 07:12:34 AM UTC 24 |
Sep 09 07:12:40 AM UTC 24 |
2480800348 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1306995219 |
|
|
Sep 09 07:11:06 AM UTC 24 |
Sep 09 07:12:41 AM UTC 24 |
70510974973 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.3230394991 |
|
|
Sep 09 07:12:31 AM UTC 24 |
Sep 09 07:12:41 AM UTC 24 |
5774559356 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.2254426292 |
|
|
Sep 09 07:12:33 AM UTC 24 |
Sep 09 07:12:41 AM UTC 24 |
2013160067 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.318242251 |
|
|
Sep 09 07:12:39 AM UTC 24 |
Sep 09 07:12:43 AM UTC 24 |
3219217858 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3373478454 |
|
|
Sep 09 07:12:39 AM UTC 24 |
Sep 09 07:12:43 AM UTC 24 |
2676420435 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.99398046 |
|
|
Sep 09 07:12:34 AM UTC 24 |
Sep 09 07:12:46 AM UTC 24 |
2109937978 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.1832866884 |
|
|
Sep 09 07:12:42 AM UTC 24 |
Sep 09 07:12:47 AM UTC 24 |
2485403112 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3183054306 |
|
|
Sep 09 07:12:42 AM UTC 24 |
Sep 09 07:12:48 AM UTC 24 |
2126405679 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.1914310328 |
|
|
Sep 09 07:12:42 AM UTC 24 |
Sep 09 07:12:49 AM UTC 24 |
2016108504 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.3180260894 |
|
|
Sep 09 07:12:44 AM UTC 24 |
Sep 09 07:12:49 AM UTC 24 |
2537564298 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.987317842 |
|
|
Sep 09 07:12:43 AM UTC 24 |
Sep 09 07:12:50 AM UTC 24 |
2064584076 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1966571831 |
|
|
Sep 09 07:12:37 AM UTC 24 |
Sep 09 07:12:51 AM UTC 24 |
2608532621 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.2157875172 |
|
|
Sep 09 07:12:37 AM UTC 24 |
Sep 09 07:12:51 AM UTC 24 |
2509470728 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1022202995 |
|
|
Sep 09 07:12:32 AM UTC 24 |
Sep 09 07:12:51 AM UTC 24 |
5277532128 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.420764484 |
|
|
Sep 09 07:12:48 AM UTC 24 |
Sep 09 07:12:53 AM UTC 24 |
2931048316 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.4251198902 |
|
|
Sep 09 07:12:49 AM UTC 24 |
Sep 09 07:12:54 AM UTC 24 |
3153352378 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3623849600 |
|
|
Sep 09 07:12:41 AM UTC 24 |
Sep 09 07:12:54 AM UTC 24 |
14422340796 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2555742539 |
|
|
Sep 09 07:12:40 AM UTC 24 |
Sep 09 07:12:56 AM UTC 24 |
7056486099 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.2444608703 |
|
|
Sep 09 07:11:05 AM UTC 24 |
Sep 09 07:12:57 AM UTC 24 |
134747649668 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3725438993 |
|
|
Sep 09 07:11:13 AM UTC 24 |
Sep 09 07:12:57 AM UTC 24 |
132134152312 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.772351172 |
|
|
Sep 09 07:11:34 AM UTC 24 |
Sep 09 07:12:57 AM UTC 24 |
112386114901 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3295773016 |
|
|
Sep 09 07:12:51 AM UTC 24 |
Sep 09 07:12:58 AM UTC 24 |
3563540274 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.3660001189 |
|
|
Sep 09 07:12:56 AM UTC 24 |
Sep 09 07:12:58 AM UTC 24 |
2211658220 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4148852074 |
|
|
Sep 09 07:12:47 AM UTC 24 |
Sep 09 07:13:00 AM UTC 24 |
2611893822 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.988935682 |
|
|
Sep 09 07:12:56 AM UTC 24 |
Sep 09 07:13:01 AM UTC 24 |
2487831522 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.785446254 |
|
|
Sep 09 07:12:57 AM UTC 24 |
Sep 09 07:13:01 AM UTC 24 |
2533503939 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2323725587 |
|
|
Sep 09 07:12:50 AM UTC 24 |
Sep 09 07:13:01 AM UTC 24 |
9501322831 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2775146228 |
|
|
Sep 09 07:12:56 AM UTC 24 |
Sep 09 07:13:02 AM UTC 24 |
2118151166 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1210181797 |
|
|
Sep 09 07:12:58 AM UTC 24 |
Sep 09 07:13:03 AM UTC 24 |
3500158880 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2827354886 |
|
|
Sep 09 07:12:58 AM UTC 24 |
Sep 09 07:13:03 AM UTC 24 |
2624821060 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.4011785227 |
|
|
Sep 09 07:12:10 AM UTC 24 |
Sep 09 07:13:05 AM UTC 24 |
66700586856 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1615636484 |
|
|
Sep 09 07:12:15 AM UTC 24 |
Sep 09 07:13:06 AM UTC 24 |
315141645093 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.1917579542 |
|
|
Sep 09 07:13:03 AM UTC 24 |
Sep 09 07:13:08 AM UTC 24 |
2032772671 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1872045643 |
|
|
Sep 09 07:13:00 AM UTC 24 |
Sep 09 07:13:08 AM UTC 24 |
2684780053 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3448351260 |
|
|
Sep 09 07:12:51 AM UTC 24 |
Sep 09 07:13:08 AM UTC 24 |
18175364682 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3509671845 |
|
|
Sep 09 07:12:59 AM UTC 24 |
Sep 09 07:13:10 AM UTC 24 |
5975391518 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.1281773655 |
|
|
Sep 09 07:13:04 AM UTC 24 |
Sep 09 07:13:11 AM UTC 24 |
2112778664 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.3774701648 |
|
|
Sep 09 07:12:01 AM UTC 24 |
Sep 09 07:13:12 AM UTC 24 |
129903562612 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.1342458714 |
|
|
Sep 09 07:12:31 AM UTC 24 |
Sep 09 07:13:13 AM UTC 24 |
28869729646 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2989297569 |
|
|
Sep 09 07:13:02 AM UTC 24 |
Sep 09 07:13:14 AM UTC 24 |
21729451657 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.999104690 |
|
|
Sep 09 07:11:20 AM UTC 24 |
Sep 09 07:13:15 AM UTC 24 |
69423763196 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.2694029607 |
|
|
Sep 09 07:13:04 AM UTC 24 |
Sep 09 07:13:15 AM UTC 24 |
2453463986 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.747177839 |
|
|
Sep 09 07:13:04 AM UTC 24 |
Sep 09 07:13:15 AM UTC 24 |
2112719211 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3166193523 |
|
|
Sep 09 07:13:07 AM UTC 24 |
Sep 09 07:13:15 AM UTC 24 |
2615336473 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2900908072 |
|
|
Sep 09 07:13:08 AM UTC 24 |
Sep 09 07:13:16 AM UTC 24 |
3554005297 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.531221137 |
|
|
Sep 09 07:13:12 AM UTC 24 |
Sep 09 07:13:16 AM UTC 24 |
2791602972 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.1147081941 |
|
|
Sep 09 07:13:06 AM UTC 24 |
Sep 09 07:13:17 AM UTC 24 |
2510048573 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.1023169170 |
|
|
Sep 09 07:13:16 AM UTC 24 |
Sep 09 07:13:18 AM UTC 24 |
2129146290 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1037755253 |
|
|
Sep 09 07:12:59 AM UTC 24 |
Sep 09 07:13:19 AM UTC 24 |
43710579420 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.181044101 |
|
|
Sep 09 07:13:34 AM UTC 24 |
Sep 09 07:13:48 AM UTC 24 |
2466805973 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.3815423344 |
|
|
Sep 09 07:12:08 AM UTC 24 |
Sep 09 07:13:19 AM UTC 24 |
90055885705 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2855301256 |
|
|
Sep 09 07:13:09 AM UTC 24 |
Sep 09 07:13:19 AM UTC 24 |
7146124388 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.516904340 |
|
|
Sep 09 07:13:16 AM UTC 24 |
Sep 09 07:13:20 AM UTC 24 |
2212637684 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1494431690 |
|
|
Sep 09 07:13:16 AM UTC 24 |
Sep 09 07:13:21 AM UTC 24 |
2478105474 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1757758039 |
|
|
Sep 09 07:12:58 AM UTC 24 |
Sep 09 07:13:22 AM UTC 24 |
4996883352 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.4270146352 |
|
|
Sep 09 07:13:16 AM UTC 24 |
Sep 09 07:13:22 AM UTC 24 |
2117167223 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3069042507 |
|
|
Sep 09 07:11:51 AM UTC 24 |
Sep 09 07:13:23 AM UTC 24 |
62862494028 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1445209746 |
|
|
Sep 09 07:13:08 AM UTC 24 |
Sep 09 07:13:24 AM UTC 24 |
3540699473 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.4162911752 |
|
|
Sep 09 07:13:20 AM UTC 24 |
Sep 09 07:13:25 AM UTC 24 |
2533527874 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2714706946 |
|
|
Sep 09 07:13:18 AM UTC 24 |
Sep 09 07:13:25 AM UTC 24 |
2801234064 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1661210496 |
|
|
Sep 09 07:13:18 AM UTC 24 |
Sep 09 07:13:26 AM UTC 24 |
2611466816 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.2110988413 |
|
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Sep 09 07:13:24 AM UTC 24 |
Sep 09 07:13:28 AM UTC 24 |
2140676229 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2283443138 |
|
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Sep 09 07:13:14 AM UTC 24 |
Sep 09 07:13:28 AM UTC 24 |
20778638772 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.2940642282 |
|
|
Sep 09 07:13:16 AM UTC 24 |
Sep 09 07:13:29 AM UTC 24 |
2511752392 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.2906363253 |
|
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Sep 09 07:13:23 AM UTC 24 |
Sep 09 07:13:30 AM UTC 24 |
2117080654 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.4136841010 |
|
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Sep 09 07:12:41 AM UTC 24 |
Sep 09 07:13:31 AM UTC 24 |
80002738461 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.712966897 |
|
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Sep 09 07:13:23 AM UTC 24 |
Sep 09 07:13:32 AM UTC 24 |
2453307512 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.3544382816 |
|
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Sep 09 07:13:28 AM UTC 24 |
Sep 09 07:13:33 AM UTC 24 |
6360281767 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.2949084633 |
|
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Sep 09 07:13:25 AM UTC 24 |
Sep 09 07:13:33 AM UTC 24 |
2616742025 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.3681106387 |
|
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Sep 09 07:13:25 AM UTC 24 |
Sep 09 07:13:33 AM UTC 24 |
2517305086 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.208004007 |
|
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Sep 09 07:13:23 AM UTC 24 |
Sep 09 07:13:34 AM UTC 24 |
2011044136 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.199388681 |
|
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Sep 09 07:13:20 AM UTC 24 |
Sep 09 07:13:35 AM UTC 24 |
10306799126 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1741599730 |
|
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Sep 09 07:13:27 AM UTC 24 |
Sep 09 07:13:36 AM UTC 24 |
3161050244 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.3156114557 |
|
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Sep 09 07:13:15 AM UTC 24 |
Sep 09 07:13:38 AM UTC 24 |
10300270293 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2696215130 |
|
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Sep 09 07:13:34 AM UTC 24 |
Sep 09 07:13:38 AM UTC 24 |
2177293458 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.442779242 |
|
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Sep 09 07:13:34 AM UTC 24 |
Sep 09 07:13:39 AM UTC 24 |
2032250642 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2173945586 |
|
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Sep 09 07:13:26 AM UTC 24 |
Sep 09 07:13:39 AM UTC 24 |
4297902491 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.3260398897 |
|
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Sep 09 07:13:30 AM UTC 24 |
Sep 09 07:13:40 AM UTC 24 |
4807804362 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2331605317 |
|
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Sep 09 07:13:37 AM UTC 24 |
Sep 09 07:13:41 AM UTC 24 |
2636413806 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.3777341290 |
|
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Sep 09 07:13:34 AM UTC 24 |
Sep 09 07:13:41 AM UTC 24 |
2119938468 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.947702590 |
|
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Sep 09 07:12:52 AM UTC 24 |
Sep 09 07:13:41 AM UTC 24 |
17263500015 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2880143360 |
|
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Sep 09 07:13:22 AM UTC 24 |
Sep 09 07:13:42 AM UTC 24 |
3652378270 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3342455524 |
|
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Sep 09 07:13:40 AM UTC 24 |
Sep 09 07:13:43 AM UTC 24 |
3947250703 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.488392103 |
|
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Sep 09 07:13:36 AM UTC 24 |
Sep 09 07:13:44 AM UTC 24 |
2516022227 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3317426638 |
|
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Sep 09 07:13:40 AM UTC 24 |
Sep 09 07:13:45 AM UTC 24 |
3381154639 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.1055872920 |
|
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Sep 09 07:13:43 AM UTC 24 |
Sep 09 07:13:47 AM UTC 24 |
2046420048 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.3010306637 |
|
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Sep 09 07:13:44 AM UTC 24 |
Sep 09 07:13:48 AM UTC 24 |
2137198141 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2450735668 |
|
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Sep 09 07:13:40 AM UTC 24 |
Sep 09 07:13:49 AM UTC 24 |
9413233163 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.665266820 |
|
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Sep 09 07:12:51 AM UTC 24 |
Sep 09 07:13:49 AM UTC 24 |
77635542844 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3307843784 |
|
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Sep 09 07:13:32 AM UTC 24 |
Sep 09 07:13:50 AM UTC 24 |
3504740415 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.3513396727 |
|
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Sep 09 07:13:47 AM UTC 24 |
Sep 09 07:13:50 AM UTC 24 |
2562116429 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.1933021851 |
|
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Sep 09 07:13:46 AM UTC 24 |
Sep 09 07:13:53 AM UTC 24 |
2255686103 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2891052356 |
|
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Sep 09 07:12:17 AM UTC 24 |
Sep 09 07:13:53 AM UTC 24 |
56190538937 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3707785210 |
|
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Sep 09 07:13:49 AM UTC 24 |
Sep 09 07:13:53 AM UTC 24 |
2629406750 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.3634227106 |
|
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Sep 09 07:13:42 AM UTC 24 |
Sep 09 07:13:54 AM UTC 24 |
4403965591 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.627225514 |
|
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Sep 09 07:13:50 AM UTC 24 |
Sep 09 07:13:56 AM UTC 24 |
3741999295 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.3264282490 |
|
|
Sep 09 07:10:50 AM UTC 24 |
Sep 09 07:13:56 AM UTC 24 |
70575381680 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2026078247 |
|
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Sep 09 07:13:01 AM UTC 24 |
Sep 09 07:13:56 AM UTC 24 |
68983358822 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1548882059 |
|
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Sep 09 07:12:25 AM UTC 24 |
Sep 09 07:13:56 AM UTC 24 |
29329615670 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3966512846 |
|
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Sep 09 07:13:42 AM UTC 24 |
Sep 09 07:13:56 AM UTC 24 |
12904745393 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.3970029572 |
|
|
Sep 09 07:13:44 AM UTC 24 |
Sep 09 07:13:58 AM UTC 24 |
2448058455 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.425682699 |
|
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Sep 09 07:13:33 AM UTC 24 |
Sep 09 07:13:58 AM UTC 24 |
10076001632 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.4275621897 |
|
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Sep 09 07:13:57 AM UTC 24 |
Sep 09 07:14:00 AM UTC 24 |
2128117412 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.606443534 |
|
|
Sep 09 07:13:51 AM UTC 24 |
Sep 09 07:14:00 AM UTC 24 |
3462593398 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.2927054040 |
|
|
Sep 09 07:13:54 AM UTC 24 |
Sep 09 07:14:00 AM UTC 24 |
2025483043 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1213334824 |
|
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Sep 09 07:11:34 AM UTC 24 |
Sep 09 07:14:02 AM UTC 24 |
47653436291 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1803030464 |
|
|
Sep 09 07:13:50 AM UTC 24 |
Sep 09 07:14:02 AM UTC 24 |
4412310001 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.2943919281 |
|
|
Sep 09 07:13:58 AM UTC 24 |
Sep 09 07:14:02 AM UTC 24 |
2521740542 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.952383930 |
|
|
Sep 09 07:13:59 AM UTC 24 |
Sep 09 07:14:03 AM UTC 24 |
3934100464 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3587549540 |
|
|
Sep 09 07:13:42 AM UTC 24 |
Sep 09 07:14:03 AM UTC 24 |
5467503273 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.775692270 |
|
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Sep 09 07:13:59 AM UTC 24 |
Sep 09 07:14:03 AM UTC 24 |
2904652990 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1314264462 |
|
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Sep 09 07:12:22 AM UTC 24 |
Sep 09 07:14:28 AM UTC 24 |
216228045563 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3629380845 |
|
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Sep 09 07:11:49 AM UTC 24 |
Sep 09 07:14:04 AM UTC 24 |
179578571628 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.508856227 |
|
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Sep 09 07:13:57 AM UTC 24 |
Sep 09 07:14:05 AM UTC 24 |
2466823964 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.558715268 |
|
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Sep 09 07:14:00 AM UTC 24 |
Sep 09 07:14:05 AM UTC 24 |
5379473080 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1091725936 |
|
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Sep 09 07:12:15 AM UTC 24 |
Sep 09 07:14:06 AM UTC 24 |
66011609985 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.980477523 |
|
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Sep 09 07:13:57 AM UTC 24 |
Sep 09 07:14:06 AM UTC 24 |
2119402594 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.3014727754 |
|
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Sep 09 07:14:04 AM UTC 24 |
Sep 09 07:14:07 AM UTC 24 |
2044717809 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.1158144087 |
|
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Sep 09 07:14:04 AM UTC 24 |
Sep 09 07:14:07 AM UTC 24 |
2262208751 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1402816843 |
|
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Sep 09 07:13:58 AM UTC 24 |
Sep 09 07:14:07 AM UTC 24 |
2614596109 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1626693594 |
|
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Sep 09 07:13:50 AM UTC 24 |
Sep 09 07:14:07 AM UTC 24 |
3540467644 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.492908344 |
|
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Sep 09 07:14:04 AM UTC 24 |
Sep 09 07:14:08 AM UTC 24 |
2496130174 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.4257490378 |
|
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Sep 09 07:12:31 AM UTC 24 |
Sep 09 07:14:08 AM UTC 24 |
192171141580 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.1548642735 |
|
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Sep 09 07:14:03 AM UTC 24 |
Sep 09 07:14:09 AM UTC 24 |
9434122697 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.1605658753 |
|
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Sep 09 07:14:05 AM UTC 24 |
Sep 09 07:14:09 AM UTC 24 |
2540642536 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.932639771 |
|
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Sep 09 07:14:06 AM UTC 24 |
Sep 09 07:14:10 AM UTC 24 |
2651871779 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1036243092 |
|
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Sep 09 07:14:06 AM UTC 24 |
Sep 09 07:14:10 AM UTC 24 |
4454263121 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.4027012739 |
|
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Sep 09 07:14:04 AM UTC 24 |
Sep 09 07:14:10 AM UTC 24 |
2113076053 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1857099370 |
|
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Sep 09 07:14:03 AM UTC 24 |
Sep 09 07:14:10 AM UTC 24 |
6086824289 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.3075472651 |
|
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Sep 09 07:14:09 AM UTC 24 |
Sep 09 07:14:11 AM UTC 24 |
2207507062 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.3128337111 |
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Sep 09 07:14:01 AM UTC 24 |
Sep 09 07:14:11 AM UTC 24 |
3403430058 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1854414755 |
|
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Sep 09 07:14:06 AM UTC 24 |
Sep 09 07:14:12 AM UTC 24 |
3732095403 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.2455393249 |
|
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Sep 09 07:14:10 AM UTC 24 |
Sep 09 07:14:13 AM UTC 24 |
2124373917 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.2269528336 |
|
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Sep 09 07:14:10 AM UTC 24 |
Sep 09 07:14:13 AM UTC 24 |
2501805620 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2868418275 |
|
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Sep 09 07:13:54 AM UTC 24 |
Sep 09 07:14:14 AM UTC 24 |
9464837113 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.1482801635 |
|
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Sep 09 07:14:11 AM UTC 24 |
Sep 09 07:14:15 AM UTC 24 |
2132209719 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4058806091 |
|
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Sep 09 07:14:13 AM UTC 24 |
Sep 09 07:14:15 AM UTC 24 |
10017654828 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.271208956 |
|
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Sep 09 07:14:11 AM UTC 24 |
Sep 09 07:14:16 AM UTC 24 |
4269226799 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1433815745 |
|
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Sep 09 07:14:13 AM UTC 24 |
Sep 09 07:14:16 AM UTC 24 |
3963625490 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2463127989 |
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Sep 09 07:14:06 AM UTC 24 |
Sep 09 07:14:16 AM UTC 24 |
2547789627 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3600290124 |
|
|
Sep 09 07:14:09 AM UTC 24 |
Sep 09 07:14:18 AM UTC 24 |
11502353798 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.74981856 |
|
|
Sep 09 07:12:51 AM UTC 24 |
Sep 09 07:14:18 AM UTC 24 |
48264581717 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.3818150050 |
|
|
Sep 09 07:14:09 AM UTC 24 |
Sep 09 07:14:19 AM UTC 24 |
7663177990 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.365250708 |
|
|
Sep 09 07:14:11 AM UTC 24 |
Sep 09 07:14:20 AM UTC 24 |
2512930620 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2854084534 |
|
|
Sep 09 07:13:31 AM UTC 24 |
Sep 09 07:14:20 AM UTC 24 |
74980858933 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.1021107839 |
|
|
Sep 09 07:14:08 AM UTC 24 |
Sep 09 07:14:20 AM UTC 24 |
2898834656 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2392910554 |
|
|
Sep 09 07:14:16 AM UTC 24 |
Sep 09 07:14:21 AM UTC 24 |
2122061034 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.1076912112 |
|
|
Sep 09 07:09:35 AM UTC 24 |
Sep 09 07:14:21 AM UTC 24 |
107893209852 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.3853052388 |
|
|
Sep 09 07:10:02 AM UTC 24 |
Sep 09 07:14:21 AM UTC 24 |
281485266889 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2553053962 |
|
|
Sep 09 07:14:11 AM UTC 24 |
Sep 09 07:14:22 AM UTC 24 |
2611797806 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3054034905 |
|
|
Sep 09 07:14:17 AM UTC 24 |
Sep 09 07:14:22 AM UTC 24 |
2057587622 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.4042397674 |
|
|
Sep 09 07:14:14 AM UTC 24 |
Sep 09 07:14:22 AM UTC 24 |
3011692550 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.434563737 |
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Sep 09 07:14:17 AM UTC 24 |
Sep 09 07:14:22 AM UTC 24 |
2469231568 ps |