| T128 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.985151474 |
|
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Sep 09 07:09:39 AM UTC 24 |
Sep 09 07:14:22 AM UTC 24 |
82246776621 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.764177616 |
|
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Sep 09 07:14:18 AM UTC 24 |
Sep 09 07:14:23 AM UTC 24 |
2531187686 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3825043869 |
|
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Sep 09 07:14:20 AM UTC 24 |
Sep 09 07:14:24 AM UTC 24 |
2786623180 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1467445329 |
|
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Sep 09 07:14:15 AM UTC 24 |
Sep 09 07:14:25 AM UTC 24 |
10672417220 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.654052836 |
|
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Sep 09 07:14:16 AM UTC 24 |
Sep 09 07:14:27 AM UTC 24 |
2013493406 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.1772212666 |
|
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Sep 09 07:14:22 AM UTC 24 |
Sep 09 07:14:28 AM UTC 24 |
3044443321 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.2696637549 |
|
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Sep 09 07:14:25 AM UTC 24 |
Sep 09 07:14:29 AM UTC 24 |
2520265202 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2829328439 |
|
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Sep 09 07:14:23 AM UTC 24 |
Sep 09 07:14:29 AM UTC 24 |
2120708034 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2881935206 |
|
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Sep 09 07:14:26 AM UTC 24 |
Sep 09 07:14:30 AM UTC 24 |
3730653743 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.1399755782 |
|
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Sep 09 07:14:23 AM UTC 24 |
Sep 09 07:14:30 AM UTC 24 |
2023457914 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.607631075 |
|
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Sep 09 07:14:21 AM UTC 24 |
Sep 09 07:14:31 AM UTC 24 |
3383979035 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.568560563 |
|
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Sep 09 07:14:25 AM UTC 24 |
Sep 09 07:14:31 AM UTC 24 |
2622562646 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3647801344 |
|
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Sep 09 07:14:21 AM UTC 24 |
Sep 09 07:14:31 AM UTC 24 |
330452394531 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.251074076 |
|
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Sep 09 07:10:27 AM UTC 24 |
Sep 09 07:14:32 AM UTC 24 |
89876032561 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.23024661 |
|
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Sep 09 07:14:24 AM UTC 24 |
Sep 09 07:14:32 AM UTC 24 |
2086536142 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.591772535 |
|
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Sep 09 07:09:56 AM UTC 24 |
Sep 09 07:14:33 AM UTC 24 |
96511820816 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2959184410 |
|
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Sep 09 07:14:20 AM UTC 24 |
Sep 09 07:14:33 AM UTC 24 |
2612835484 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.3759652699 |
|
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Sep 09 07:13:51 AM UTC 24 |
Sep 09 07:14:36 AM UTC 24 |
30366834160 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.2207160459 |
|
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Sep 09 07:14:33 AM UTC 24 |
Sep 09 07:14:36 AM UTC 24 |
2163939405 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.153427138 |
|
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Sep 09 07:14:29 AM UTC 24 |
Sep 09 07:14:36 AM UTC 24 |
189072242960 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.100193784 |
|
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Sep 09 07:13:14 AM UTC 24 |
Sep 09 07:14:36 AM UTC 24 |
26781821990 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.4278481480 |
|
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Sep 09 07:14:33 AM UTC 24 |
Sep 09 07:14:37 AM UTC 24 |
2494128400 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.52987490 |
|
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Sep 09 07:14:32 AM UTC 24 |
Sep 09 07:14:37 AM UTC 24 |
2025089285 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2111554881 |
|
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Sep 09 07:14:33 AM UTC 24 |
Sep 09 07:14:38 AM UTC 24 |
2521853970 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.201113133 |
|
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Sep 09 07:14:33 AM UTC 24 |
Sep 09 07:14:40 AM UTC 24 |
2114532396 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.1386482470 |
|
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Sep 09 07:14:31 AM UTC 24 |
Sep 09 07:14:40 AM UTC 24 |
7813387689 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.2020634207 |
|
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Sep 09 07:14:30 AM UTC 24 |
Sep 09 07:14:40 AM UTC 24 |
3000364217 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.2825574344 |
|
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Sep 09 07:14:23 AM UTC 24 |
Sep 09 07:14:40 AM UTC 24 |
2473731356 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1717348583 |
|
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Sep 09 07:14:37 AM UTC 24 |
Sep 09 07:14:40 AM UTC 24 |
2982652170 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3119705641 |
|
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Sep 09 07:14:28 AM UTC 24 |
Sep 09 07:14:42 AM UTC 24 |
3503041829 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2998714185 |
|
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Sep 09 07:14:31 AM UTC 24 |
Sep 09 07:14:43 AM UTC 24 |
13134172916 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.4038906174 |
|
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Sep 09 07:13:42 AM UTC 24 |
Sep 09 07:14:45 AM UTC 24 |
22582350517 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2264965383 |
|
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Sep 09 07:14:34 AM UTC 24 |
Sep 09 07:14:46 AM UTC 24 |
3727228646 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2056154378 |
|
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Sep 09 07:14:40 AM UTC 24 |
Sep 09 07:14:46 AM UTC 24 |
13750351274 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.3106055698 |
|
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Sep 09 07:14:22 AM UTC 24 |
Sep 09 07:14:46 AM UTC 24 |
9052854907 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1380412398 |
|
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Sep 09 07:14:34 AM UTC 24 |
Sep 09 07:14:47 AM UTC 24 |
2612566193 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2237894602 |
|
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Sep 09 07:12:41 AM UTC 24 |
Sep 09 07:14:47 AM UTC 24 |
41184429236 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.3771091890 |
|
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Sep 09 07:13:54 AM UTC 24 |
Sep 09 07:14:47 AM UTC 24 |
13484159133 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.249888502 |
|
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Sep 09 07:14:41 AM UTC 24 |
Sep 09 07:14:47 AM UTC 24 |
2117051150 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.1631299693 |
|
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Sep 09 07:14:41 AM UTC 24 |
Sep 09 07:14:47 AM UTC 24 |
2021649852 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2177333117 |
|
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Sep 09 07:14:41 AM UTC 24 |
Sep 09 07:14:48 AM UTC 24 |
2468117020 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.578617299 |
|
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Sep 09 07:14:22 AM UTC 24 |
Sep 09 07:14:49 AM UTC 24 |
17187525430 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.3893973959 |
|
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Sep 09 07:14:41 AM UTC 24 |
Sep 09 07:14:49 AM UTC 24 |
2513038700 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.4016531473 |
|
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Sep 09 07:14:36 AM UTC 24 |
Sep 09 07:14:50 AM UTC 24 |
3222341874 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.549474712 |
|
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Sep 09 07:14:48 AM UTC 24 |
Sep 09 07:14:51 AM UTC 24 |
2039731767 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1283778420 |
|
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Sep 09 07:14:46 AM UTC 24 |
Sep 09 07:14:52 AM UTC 24 |
3457790715 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1423933760 |
|
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Sep 09 07:14:38 AM UTC 24 |
Sep 09 07:14:52 AM UTC 24 |
6085082591 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.3814748240 |
|
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Sep 09 07:14:49 AM UTC 24 |
Sep 09 07:14:53 AM UTC 24 |
2134477170 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.120139043 |
|
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Sep 09 07:14:43 AM UTC 24 |
Sep 09 07:14:53 AM UTC 24 |
2609941691 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.3374851931 |
|
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Sep 09 07:14:41 AM UTC 24 |
Sep 09 07:14:54 AM UTC 24 |
2203923413 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.791507095 |
|
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Sep 09 07:14:49 AM UTC 24 |
Sep 09 07:14:54 AM UTC 24 |
2462319050 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.2385326951 |
|
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Sep 09 07:14:50 AM UTC 24 |
Sep 09 07:14:55 AM UTC 24 |
2223313559 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.1347327371 |
|
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Sep 09 07:14:50 AM UTC 24 |
Sep 09 07:14:55 AM UTC 24 |
2524182102 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2432445165 |
|
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Sep 09 07:14:16 AM UTC 24 |
Sep 09 07:14:56 AM UTC 24 |
53689349118 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1913802492 |
|
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Sep 09 07:14:52 AM UTC 24 |
Sep 09 07:14:57 AM UTC 24 |
2766404159 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.107478727 |
|
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Sep 09 07:14:48 AM UTC 24 |
Sep 09 07:14:59 AM UTC 24 |
33925563565 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.4195325066 |
|
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Sep 09 07:14:48 AM UTC 24 |
Sep 09 07:14:59 AM UTC 24 |
3460406344 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2847128643 |
|
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Sep 09 07:14:51 AM UTC 24 |
Sep 09 07:14:59 AM UTC 24 |
2615927538 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1171646356 |
|
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Sep 09 07:14:46 AM UTC 24 |
Sep 09 07:14:59 AM UTC 24 |
5412083614 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.562307092 |
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Sep 09 07:14:48 AM UTC 24 |
Sep 09 07:14:59 AM UTC 24 |
3220792960 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2601010264 |
|
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Sep 09 07:14:57 AM UTC 24 |
Sep 09 07:15:00 AM UTC 24 |
2154508493 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1095754385 |
|
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Sep 09 07:14:54 AM UTC 24 |
Sep 09 07:15:01 AM UTC 24 |
4915672455 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1218039587 |
|
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Sep 09 07:13:54 AM UTC 24 |
Sep 09 07:15:02 AM UTC 24 |
23330878735 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2503769383 |
|
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Sep 09 07:15:00 AM UTC 24 |
Sep 09 07:15:03 AM UTC 24 |
2664979467 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.1067153708 |
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Sep 09 07:14:56 AM UTC 24 |
Sep 09 07:15:03 AM UTC 24 |
2009087012 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.1978126228 |
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Sep 09 07:14:59 AM UTC 24 |
Sep 09 07:15:04 AM UTC 24 |
2245500710 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.2899468185 |
|
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Sep 09 07:14:59 AM UTC 24 |
Sep 09 07:15:04 AM UTC 24 |
2524183450 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.268611251 |
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Sep 09 07:10:19 AM UTC 24 |
Sep 09 07:15:05 AM UTC 24 |
104920595517 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1140013228 |
|
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Sep 09 07:15:01 AM UTC 24 |
Sep 09 07:15:06 AM UTC 24 |
3214895338 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1622833698 |
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Sep 09 07:14:55 AM UTC 24 |
Sep 09 07:15:07 AM UTC 24 |
8785188891 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.2370492751 |
|
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Sep 09 07:14:58 AM UTC 24 |
Sep 09 07:15:07 AM UTC 24 |
2448021589 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1141426305 |
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Sep 09 07:15:03 AM UTC 24 |
Sep 09 07:15:08 AM UTC 24 |
4851058943 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.1889952388 |
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Sep 09 07:15:05 AM UTC 24 |
Sep 09 07:15:09 AM UTC 24 |
2031471839 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.1190221095 |
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Sep 09 07:13:03 AM UTC 24 |
Sep 09 07:15:11 AM UTC 24 |
100376139345 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1552802274 |
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Sep 09 07:15:01 AM UTC 24 |
Sep 09 07:15:11 AM UTC 24 |
9782814007 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.1141447150 |
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Sep 09 07:15:08 AM UTC 24 |
Sep 09 07:15:12 AM UTC 24 |
2497381993 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.4020509009 |
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Sep 09 07:15:01 AM UTC 24 |
Sep 09 07:15:13 AM UTC 24 |
3724546213 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.1304129671 |
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Sep 09 07:14:56 AM UTC 24 |
Sep 09 07:15:14 AM UTC 24 |
15623347264 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.1603194877 |
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Sep 09 07:16:13 AM UTC 24 |
Sep 09 07:16:18 AM UTC 24 |
2113015617 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.97581640 |
|
|
Sep 09 07:14:37 AM UTC 24 |
Sep 09 07:16:19 AM UTC 24 |
1021404679650 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3926682634 |
|
|
Sep 09 07:16:06 AM UTC 24 |
Sep 09 07:16:22 AM UTC 24 |
4130448469 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2357036300 |
|
|
Sep 09 07:15:12 AM UTC 24 |
Sep 09 07:15:16 AM UTC 24 |
3778432901 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.4167539167 |
|
|
Sep 09 07:15:08 AM UTC 24 |
Sep 09 07:15:17 AM UTC 24 |
2163675537 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.49627134 |
|
|
Sep 09 07:15:05 AM UTC 24 |
Sep 09 07:15:17 AM UTC 24 |
2109897710 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3974700833 |
|
|
Sep 09 07:15:09 AM UTC 24 |
Sep 09 07:15:18 AM UTC 24 |
2510410527 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.3079053835 |
|
|
Sep 09 07:14:37 AM UTC 24 |
Sep 09 07:15:18 AM UTC 24 |
26332896519 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.1508429575 |
|
|
Sep 09 07:11:40 AM UTC 24 |
Sep 09 07:15:19 AM UTC 24 |
68801372122 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.3415190110 |
|
|
Sep 09 07:15:14 AM UTC 24 |
Sep 09 07:15:19 AM UTC 24 |
3144875440 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.4225122603 |
|
|
Sep 09 07:15:17 AM UTC 24 |
Sep 09 07:15:20 AM UTC 24 |
2030257017 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.442348559 |
|
|
Sep 09 07:12:11 AM UTC 24 |
Sep 09 07:15:20 AM UTC 24 |
150436885679 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2611675230 |
|
|
Sep 09 07:15:09 AM UTC 24 |
Sep 09 07:15:23 AM UTC 24 |
2612112070 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3131682407 |
|
|
Sep 09 07:15:20 AM UTC 24 |
Sep 09 07:15:23 AM UTC 24 |
2643729575 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.2251962267 |
|
|
Sep 09 07:15:19 AM UTC 24 |
Sep 09 07:15:24 AM UTC 24 |
2470010201 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.3602639788 |
|
|
Sep 09 07:15:16 AM UTC 24 |
Sep 09 07:15:25 AM UTC 24 |
17122667331 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.2115023844 |
|
|
Sep 09 07:15:20 AM UTC 24 |
Sep 09 07:15:26 AM UTC 24 |
2525234314 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1990095544 |
|
|
Sep 09 07:15:20 AM UTC 24 |
Sep 09 07:15:26 AM UTC 24 |
3785467017 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.574595888 |
|
|
Sep 09 07:15:18 AM UTC 24 |
Sep 09 07:15:28 AM UTC 24 |
2110868076 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2790206741 |
|
|
Sep 09 07:15:21 AM UTC 24 |
Sep 09 07:15:30 AM UTC 24 |
5923621851 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2283705854 |
|
|
Sep 09 07:15:16 AM UTC 24 |
Sep 09 07:15:30 AM UTC 24 |
43764584050 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.249937345 |
|
|
Sep 09 07:15:19 AM UTC 24 |
Sep 09 07:15:30 AM UTC 24 |
2182505293 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.3668558071 |
|
|
Sep 09 07:15:27 AM UTC 24 |
Sep 09 07:15:35 AM UTC 24 |
2017081345 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.1203227021 |
|
|
Sep 09 07:15:31 AM UTC 24 |
Sep 09 07:15:36 AM UTC 24 |
2246680502 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.1153838917 |
|
|
Sep 09 07:15:31 AM UTC 24 |
Sep 09 07:15:36 AM UTC 24 |
2536388908 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.486799127 |
|
|
Sep 09 07:15:30 AM UTC 24 |
Sep 09 07:15:37 AM UTC 24 |
2460839323 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2434880842 |
|
|
Sep 09 07:15:26 AM UTC 24 |
Sep 09 07:15:39 AM UTC 24 |
4944938199 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2582991227 |
|
|
Sep 09 07:09:34 AM UTC 24 |
Sep 09 07:15:41 AM UTC 24 |
154021414306 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.3133484080 |
|
|
Sep 09 07:15:29 AM UTC 24 |
Sep 09 07:15:41 AM UTC 24 |
2107848450 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3906187248 |
|
|
Sep 09 07:10:26 AM UTC 24 |
Sep 09 07:15:42 AM UTC 24 |
107706920695 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.898771018 |
|
|
Sep 09 07:15:36 AM UTC 24 |
Sep 09 07:15:42 AM UTC 24 |
3695065801 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2198039953 |
|
|
Sep 09 07:15:38 AM UTC 24 |
Sep 09 07:15:43 AM UTC 24 |
10058625513 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.3592308271 |
|
|
Sep 09 07:15:24 AM UTC 24 |
Sep 09 07:15:43 AM UTC 24 |
4082541731 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1461433216 |
|
|
Sep 09 07:15:27 AM UTC 24 |
Sep 09 07:15:44 AM UTC 24 |
14086681109 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.921354338 |
|
|
Sep 09 07:15:35 AM UTC 24 |
Sep 09 07:15:47 AM UTC 24 |
2612246868 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.3071031867 |
|
|
Sep 09 07:15:45 AM UTC 24 |
Sep 09 07:15:49 AM UTC 24 |
2489031835 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.1682023549 |
|
|
Sep 09 07:15:44 AM UTC 24 |
Sep 09 07:15:51 AM UTC 24 |
2015625855 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3285628398 |
|
|
Sep 09 07:15:42 AM UTC 24 |
Sep 09 07:15:51 AM UTC 24 |
2857881390 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.3132303609 |
|
|
Sep 09 07:15:46 AM UTC 24 |
Sep 09 07:15:53 AM UTC 24 |
2162802675 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3115674360 |
|
|
Sep 09 07:15:37 AM UTC 24 |
Sep 09 07:15:54 AM UTC 24 |
3142522367 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.2707123200 |
|
|
Sep 09 07:15:44 AM UTC 24 |
Sep 09 07:15:54 AM UTC 24 |
2112250448 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1161454292 |
|
|
Sep 09 07:15:50 AM UTC 24 |
Sep 09 07:15:55 AM UTC 24 |
2624501034 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2511281865 |
|
|
Sep 09 07:15:52 AM UTC 24 |
Sep 09 07:15:57 AM UTC 24 |
2856379438 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2936458874 |
|
|
Sep 09 07:15:43 AM UTC 24 |
Sep 09 07:15:58 AM UTC 24 |
19810348653 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1578974309 |
|
|
Sep 09 07:15:52 AM UTC 24 |
Sep 09 07:15:59 AM UTC 24 |
4020348222 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.845901384 |
|
|
Sep 09 07:15:55 AM UTC 24 |
Sep 09 07:16:00 AM UTC 24 |
3208651097 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.2100730195 |
|
|
Sep 09 07:15:48 AM UTC 24 |
Sep 09 07:16:00 AM UTC 24 |
2507563215 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.109515712 |
|
|
Sep 09 07:14:22 AM UTC 24 |
Sep 09 07:16:03 AM UTC 24 |
52819660314 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1736716209 |
|
|
Sep 09 07:15:54 AM UTC 24 |
Sep 09 07:16:03 AM UTC 24 |
11470750650 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2024962742 |
|
|
Sep 09 07:15:25 AM UTC 24 |
Sep 09 07:16:04 AM UTC 24 |
59329597009 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.1733848196 |
|
|
Sep 09 07:12:20 AM UTC 24 |
Sep 09 07:16:06 AM UTC 24 |
142499540960 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.588953463 |
|
|
Sep 09 07:16:00 AM UTC 24 |
Sep 09 07:16:06 AM UTC 24 |
2024288543 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.4143463436 |
|
|
Sep 09 07:16:04 AM UTC 24 |
Sep 09 07:16:07 AM UTC 24 |
2621323415 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.160787089 |
|
|
Sep 09 07:10:39 AM UTC 24 |
Sep 09 07:16:08 AM UTC 24 |
127780723009 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.996680983 |
|
|
Sep 09 07:16:05 AM UTC 24 |
Sep 09 07:16:09 AM UTC 24 |
2653341324 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.908797411 |
|
|
Sep 09 07:16:13 AM UTC 24 |
Sep 09 07:16:23 AM UTC 24 |
2449627597 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.1141562268 |
|
|
Sep 09 07:14:54 AM UTC 24 |
Sep 09 07:16:09 AM UTC 24 |
107835639969 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.1274391261 |
|
|
Sep 09 07:16:01 AM UTC 24 |
Sep 09 07:16:12 AM UTC 24 |
2110303473 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1394748252 |
|
|
Sep 09 07:15:03 AM UTC 24 |
Sep 09 07:16:12 AM UTC 24 |
80555367170 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2117677874 |
|
|
Sep 09 07:16:07 AM UTC 24 |
Sep 09 07:16:12 AM UTC 24 |
5774747399 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2234691983 |
|
|
Sep 09 07:15:59 AM UTC 24 |
Sep 09 07:16:12 AM UTC 24 |
12780211309 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.4011766813 |
|
|
Sep 09 07:16:03 AM UTC 24 |
Sep 09 07:16:12 AM UTC 24 |
2262293030 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3569713074 |
|
|
Sep 09 07:09:44 AM UTC 24 |
Sep 09 07:16:13 AM UTC 24 |
133455846036 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2313654825 |
|
|
Sep 09 07:16:07 AM UTC 24 |
Sep 09 07:16:13 AM UTC 24 |
3744158870 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.244104802 |
|
|
Sep 09 07:16:10 AM UTC 24 |
Sep 09 07:16:14 AM UTC 24 |
2404607447 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3981903611 |
|
|
Sep 09 07:16:02 AM UTC 24 |
Sep 09 07:16:15 AM UTC 24 |
2460565508 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.1075341335 |
|
|
Sep 09 07:15:13 AM UTC 24 |
Sep 09 07:16:16 AM UTC 24 |
67546484827 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.2113417770 |
|
|
Sep 09 07:16:14 AM UTC 24 |
Sep 09 07:16:17 AM UTC 24 |
2109303147 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.3326798339 |
|
|
Sep 09 07:16:14 AM UTC 24 |
Sep 09 07:16:18 AM UTC 24 |
2555008254 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2021597181 |
|
|
Sep 09 07:16:15 AM UTC 24 |
Sep 09 07:16:18 AM UTC 24 |
2687528593 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.3115130792 |
|
|
Sep 09 07:16:13 AM UTC 24 |
Sep 09 07:16:19 AM UTC 24 |
2021654612 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2108438175 |
|
|
Sep 09 07:16:17 AM UTC 24 |
Sep 09 07:16:22 AM UTC 24 |
2921319029 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2037031377 |
|
|
Sep 09 07:16:19 AM UTC 24 |
Sep 09 07:16:25 AM UTC 24 |
3598601899 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.4173551371 |
|
|
Sep 09 07:15:43 AM UTC 24 |
Sep 09 07:16:25 AM UTC 24 |
26085859877 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.3028551288 |
|
|
Sep 09 07:16:22 AM UTC 24 |
Sep 09 07:16:28 AM UTC 24 |
2023155606 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.294424680 |
|
|
Sep 09 07:16:13 AM UTC 24 |
Sep 09 07:16:29 AM UTC 24 |
5288943400 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4205524487 |
|
|
Sep 09 07:15:21 AM UTC 24 |
Sep 09 07:16:29 AM UTC 24 |
67163415928 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1835443652 |
|
|
Sep 09 07:16:18 AM UTC 24 |
Sep 09 07:16:31 AM UTC 24 |
14365525673 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.1113536351 |
|
|
Sep 09 07:16:20 AM UTC 24 |
Sep 09 07:16:31 AM UTC 24 |
10720565929 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1352388204 |
|
|
Sep 09 07:16:16 AM UTC 24 |
Sep 09 07:16:34 AM UTC 24 |
4403510364 ps |
| T132 |
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Sep 09 07:14:48 AM UTC 24 |
Sep 09 07:16:35 AM UTC 24 |
1278622933418 ps |
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Sep 09 07:16:19 AM UTC 24 |
Sep 09 07:16:44 AM UTC 24 |
51491673525 ps |
| T758 |
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Sep 09 07:16:30 AM UTC 24 |
Sep 09 07:16:44 AM UTC 24 |
45920852623 ps |
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Sep 09 07:15:15 AM UTC 24 |
Sep 09 07:16:45 AM UTC 24 |
26581004553 ps |
| T760 |
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Sep 09 07:14:53 AM UTC 24 |
Sep 09 07:16:50 AM UTC 24 |
126129477975 ps |
| T761 |
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Sep 09 07:16:20 AM UTC 24 |
Sep 09 07:16:53 AM UTC 24 |
30196279566 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.637731356 |
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Sep 09 07:16:09 AM UTC 24 |
Sep 09 07:16:57 AM UTC 24 |
158163277993 ps |
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Sep 09 07:15:02 AM UTC 24 |
Sep 09 07:17:00 AM UTC 24 |
130156406226 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3197220370 |
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Sep 09 07:16:36 AM UTC 24 |
Sep 09 07:17:02 AM UTC 24 |
26600488119 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.3433462787 |
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Sep 09 07:15:24 AM UTC 24 |
Sep 09 07:17:04 AM UTC 24 |
57307521661 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1893244578 |
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Sep 09 07:12:40 AM UTC 24 |
Sep 09 07:17:04 AM UTC 24 |
91679034485 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.88610280 |
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Sep 09 07:16:13 AM UTC 24 |
Sep 09 07:17:05 AM UTC 24 |
13721158368 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.285170987 |
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Sep 09 07:14:08 AM UTC 24 |
Sep 09 07:17:09 AM UTC 24 |
113858711091 ps |
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Sep 09 07:14:44 AM UTC 24 |
Sep 09 07:17:16 AM UTC 24 |
819864715576 ps |
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Sep 09 07:16:22 AM UTC 24 |
Sep 09 07:17:19 AM UTC 24 |
45623986186 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1948700553 |
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Sep 09 07:11:12 AM UTC 24 |
Sep 09 07:17:20 AM UTC 24 |
147805768352 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.4065149076 |
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Sep 09 07:14:37 AM UTC 24 |
Sep 09 07:17:20 AM UTC 24 |
178578052426 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.3327303442 |
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Sep 09 07:15:41 AM UTC 24 |
Sep 09 07:17:23 AM UTC 24 |
91913598558 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.4231301125 |
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Sep 09 07:16:51 AM UTC 24 |
Sep 09 07:17:25 AM UTC 24 |
51796324138 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1120426496 |
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Sep 09 07:14:22 AM UTC 24 |
Sep 09 07:17:29 AM UTC 24 |
89085312149 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.2531438358 |
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Sep 09 07:14:14 AM UTC 24 |
Sep 09 07:17:29 AM UTC 24 |
95806902605 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.2736056473 |
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Sep 09 07:09:50 AM UTC 24 |
Sep 09 07:17:31 AM UTC 24 |
176906973786 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3201828909 |
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Sep 09 07:16:26 AM UTC 24 |
Sep 09 07:17:35 AM UTC 24 |
81634018468 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.429188004 |
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Sep 09 07:17:17 AM UTC 24 |
Sep 09 07:17:40 AM UTC 24 |
58003143166 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.281613857 |
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Sep 09 07:12:22 AM UTC 24 |
Sep 09 07:17:41 AM UTC 24 |
126785299405 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.2793223828 |
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Sep 09 07:10:01 AM UTC 24 |
Sep 09 07:17:42 AM UTC 24 |
167406498460 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.10978495 |
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Sep 09 07:13:30 AM UTC 24 |
Sep 09 07:17:43 AM UTC 24 |
91795922846 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.3786791612 |
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Sep 09 07:15:54 AM UTC 24 |
Sep 09 07:17:44 AM UTC 24 |
42771304155 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1502251015 |
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Sep 09 07:15:56 AM UTC 24 |
Sep 09 07:17:47 AM UTC 24 |
173406195425 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4017072257 |
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Sep 09 07:16:46 AM UTC 24 |
Sep 09 07:17:49 AM UTC 24 |
95854749447 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3731470405 |
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Sep 09 07:15:12 AM UTC 24 |
Sep 09 07:17:50 AM UTC 24 |
2996810328843 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3558453871 |
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Sep 09 07:16:56 AM UTC 24 |
Sep 09 07:17:54 AM UTC 24 |
101157707338 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.541002669 |
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Sep 09 07:17:26 AM UTC 24 |
Sep 09 07:19:08 AM UTC 24 |
112026728365 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4062340481 |
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Sep 09 07:16:54 AM UTC 24 |
Sep 09 07:17:56 AM UTC 24 |
46444504933 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2600432525 |
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Sep 09 07:17:30 AM UTC 24 |
Sep 09 07:18:01 AM UTC 24 |
24601776113 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1281150522 |
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Sep 09 07:17:19 AM UTC 24 |
Sep 09 07:18:05 AM UTC 24 |
89226434155 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.909128556 |
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Sep 09 07:13:19 AM UTC 24 |
Sep 09 07:18:08 AM UTC 24 |
220602867446 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3374131587 |
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Sep 09 07:17:43 AM UTC 24 |
Sep 09 07:18:09 AM UTC 24 |
27852904410 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2821488118 |
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Sep 09 07:16:35 AM UTC 24 |
Sep 09 07:18:10 AM UTC 24 |
51785571271 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1075879359 |
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Sep 09 07:17:01 AM UTC 24 |
Sep 09 07:18:10 AM UTC 24 |
75114163728 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1630819565 |
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Sep 09 07:17:05 AM UTC 24 |
Sep 09 07:18:11 AM UTC 24 |
89525776814 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3406436853 |
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Sep 09 07:17:32 AM UTC 24 |
Sep 09 07:18:12 AM UTC 24 |
33220238359 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.243859282 |
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Sep 09 07:16:30 AM UTC 24 |
Sep 09 07:18:13 AM UTC 24 |
57988752785 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2546938333 |
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Sep 09 07:13:20 AM UTC 24 |
Sep 09 07:18:15 AM UTC 24 |
113189928246 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.17195077 |
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Sep 09 07:10:58 AM UTC 24 |
Sep 09 07:18:16 AM UTC 24 |
161952693949 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1756235116 |
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Sep 09 07:16:19 AM UTC 24 |
Sep 09 07:18:22 AM UTC 24 |
33976310211 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.3285247117 |
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Sep 09 07:13:20 AM UTC 24 |
Sep 09 07:18:23 AM UTC 24 |
99230720005 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2692667784 |
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Sep 09 07:16:29 AM UTC 24 |
Sep 09 07:18:23 AM UTC 24 |
64982695265 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2802508033 |
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Sep 09 07:17:57 AM UTC 24 |
Sep 09 07:18:26 AM UTC 24 |
24595454017 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.42976432 |
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Sep 09 07:13:40 AM UTC 24 |
Sep 09 07:18:28 AM UTC 24 |
97934798055 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1065288549 |
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Sep 09 07:16:23 AM UTC 24 |
Sep 09 07:18:30 AM UTC 24 |
61354533300 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.22497306 |
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Sep 09 07:18:02 AM UTC 24 |
Sep 09 07:18:31 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2497484112 |
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Sep 09 07:16:32 AM UTC 24 |
Sep 09 07:18:39 AM UTC 24 |
33580417335 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1461517083 |
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Sep 09 07:17:30 AM UTC 24 |
Sep 09 07:18:40 AM UTC 24 |
59633061626 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.139200823 |
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Sep 09 07:17:50 AM UTC 24 |
Sep 09 07:18:40 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1889900560 |
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Sep 09 07:17:24 AM UTC 24 |
Sep 09 07:18:55 AM UTC 24 |
27833065476 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.868229611 |
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Sep 09 07:16:44 AM UTC 24 |
Sep 09 07:18:55 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.4132772937 |
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Sep 09 07:14:02 AM UTC 24 |
Sep 09 07:19:02 AM UTC 24 |
107118394354 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2836073096 |
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Sep 09 07:14:08 AM UTC 24 |
Sep 09 07:19:05 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2610613588 |
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Sep 09 07:17:41 AM UTC 24 |
Sep 09 07:19:10 AM UTC 24 |
56815300411 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1720573536 |
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Sep 09 07:09:28 AM UTC 24 |
Sep 09 07:19:17 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.672722583 |
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Sep 09 07:14:48 AM UTC 24 |
Sep 09 07:19:19 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.524171759 |
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Sep 09 07:11:34 AM UTC 24 |
Sep 09 07:19:23 AM UTC 24 |
169825463965 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.544483291 |
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Sep 09 07:16:44 AM UTC 24 |
Sep 09 07:19:25 AM UTC 24 |
46589734602 ps |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.607095357 |
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Sep 09 07:17:08 AM UTC 24 |
Sep 09 07:19:29 AM UTC 24 |
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Sep 09 07:13:11 AM UTC 24 |
Sep 09 07:19:33 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1518407305 |
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Sep 09 07:17:35 AM UTC 24 |
Sep 09 07:19:43 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2505565911 |
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Sep 09 07:17:12 AM UTC 24 |
Sep 09 07:19:45 AM UTC 24 |
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Sep 09 07:17:10 AM UTC 24 |
Sep 09 07:19:48 AM UTC 24 |
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Sep 09 07:17:51 AM UTC 24 |
Sep 09 07:20:03 AM UTC 24 |
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Sep 09 07:17:20 AM UTC 24 |
Sep 09 07:20:07 AM UTC 24 |
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Sep 09 07:14:29 AM UTC 24 |
Sep 09 07:20:10 AM UTC 24 |
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Sep 09 07:14:14 AM UTC 24 |
Sep 09 07:20:12 AM UTC 24 |
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Sep 09 07:17:02 AM UTC 24 |
Sep 09 07:20:30 AM UTC 24 |
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Sep 09 07:17:05 AM UTC 24 |
Sep 09 07:20:32 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2571358339 |
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Sep 09 07:17:05 AM UTC 24 |
Sep 09 07:20:36 AM UTC 24 |
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Sep 09 07:15:43 AM UTC 24 |
Sep 09 07:20:39 AM UTC 24 |
211153978043 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3145455163 |
|
|
Sep 09 07:16:32 AM UTC 24 |
Sep 09 07:20:51 AM UTC 24 |
90353981279 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.734139082 |
|
|
Sep 09 07:17:20 AM UTC 24 |
Sep 09 07:20:57 AM UTC 24 |
69576121995 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3093876316 |
|
|
Sep 09 07:18:10 AM UTC 24 |
Sep 09 07:20:58 AM UTC 24 |
106095200248 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2313670234 |
|
|
Sep 09 07:17:43 AM UTC 24 |
Sep 09 07:20:59 AM UTC 24 |
53039282614 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3803185614 |
|
|
Sep 09 07:17:55 AM UTC 24 |
Sep 09 07:21:18 AM UTC 24 |
137909995278 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2293389945 |
|
|
Sep 09 07:13:22 AM UTC 24 |
Sep 09 07:21:42 AM UTC 24 |
181011946058 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3272204131 |
|
|
Sep 09 07:17:49 AM UTC 24 |
Sep 09 07:21:43 AM UTC 24 |
68434214620 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.480832877 |
|
|
Sep 09 07:18:09 AM UTC 24 |
Sep 09 07:21:49 AM UTC 24 |
56268901814 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3518489164 |
|
|
Sep 09 07:17:41 AM UTC 24 |
Sep 09 07:22:25 AM UTC 24 |
97298428256 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2833051733 |
|
|
Sep 09 07:14:01 AM UTC 24 |
Sep 09 07:22:32 AM UTC 24 |
181645968063 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.570807104 |
|
|
Sep 09 07:18:05 AM UTC 24 |
Sep 09 07:22:34 AM UTC 24 |
94241607208 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2375921495 |
|
|
Sep 09 07:14:55 AM UTC 24 |
Sep 09 07:22:45 AM UTC 24 |
153376480954 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.3745361168 |
|
|
Sep 09 07:15:04 AM UTC 24 |
Sep 09 07:22:50 AM UTC 24 |
115077179481 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3592232718 |
|
|
Sep 09 07:17:44 AM UTC 24 |
Sep 09 07:23:57 AM UTC 24 |
129243487977 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2088310067 |
|
|
Sep 09 07:15:10 AM UTC 24 |
Sep 09 07:24:52 AM UTC 24 |
676660459506 ps |