Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1028010
Category 01028010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1028010
Severity 01028010

Summary for Assertions
NUMBERPERCENT
Total Number1028100.00
Uncovered121.17
Success101698.83
Failure00.00
Incomplete10.10
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0091291200
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001237025584232335700
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 001237025007586300
tb.dut.tlul_assert_device.gen_device.contigMask_M 001237025584867359100
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00123702558417597800
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 001237025007603000
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0012370255841024206000
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00123702558453713100
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0012370255841024206000
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00123702558453713100
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00123702558453713100
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00123702558453713100
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 001237025007369400
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 001237025007337900
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0091291200
tb.dut.u_reg.en2addrHit 00123702500724600100
tb.dut.u_reg.reAfterRv 00123702500724600000
tb.dut.u_reg.rePulse 00123702500713299300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A 00123702500793216500
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A 001237025007119000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007119000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782119000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782109000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007119600
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A 00123702500788089600
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A 001237025007112600
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007112600
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782112600
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782102400
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007113400
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0091291200
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A 001237025007146073400
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A 001237025007178300
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007178300
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782178300
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782168100
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007179000
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A 001237025007142416900
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A 001237025007173400
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007173400
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782173400
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782163200
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007174000
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A 001237025007143268400
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A 001237025007174400
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007174400
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782174400
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782164200
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007175000
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A 001237025007141756000
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A 001237025007175800
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007175800
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782175800
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782165600
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007176400
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A 001237025007146393400
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A 001237025007178700
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007178700
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782178700
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782169100
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007179400
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A 001237025007143654800
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A 001237025007175200
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007175200
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782175200
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782164700
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007175800
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A 001237025007140115500
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A 001237025007174500
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007174500
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782174500
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782164000
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007175200
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A 001237025007141748300
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A 001237025007174300
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007174300
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782174300
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782163700
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007174800
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A 001237025007104201600
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A 001237025007129200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007129200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782129200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782118800
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007129800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A 00123702500796644600
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A 001237025007125200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007125200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782125200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782114600
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007125700
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A 00123702500792737900
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A 001237025007120200
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007120200
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782120200
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782109800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007120900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A 00123702500798099700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A 001237025007126700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007126700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782126700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782116400
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007127300
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A 001237025007576529400
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A 001237025007677700
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007677700
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782677700
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782666900
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007678200
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A 001237025007581484500
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A 001237025007677900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007677900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782677900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782666900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007678300
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A 001237025007576360700
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A 001237025007679800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007679800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782679800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782669600
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007680600
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A 001237025007580711500
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A 001237025007699800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007699800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782699800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782689200
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007700400
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A 001237025007629447300
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A 001237025007730600
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007730600
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782730600
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782720500
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007731200
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A 001237025007630159000
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A 001237025007725500
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007725500
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782725500
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782715200
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007726000
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A 001237025007621819500
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A 001237025007727300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007727300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782727300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782716600
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007727900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A 001237025007629875400
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A 001237025007748400
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007748400
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782748400
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 005045782737900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001237025007748800
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A 001237025007147175100
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A 005045782439437700
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A 001237025007179200
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A 001237025007123661084800
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001237025007179200
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 005045782179200
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